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PostPosted: Thu Dec 27, 2018 3:30 am 
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I heard there are some documents that describe what the 6502 CPU is doing every cycle of each operation. Where can I find one? Also, is is possible to emulate the CPU in such way that you don't have to implement illegal opcodes separately and have them be a side effect of the coding, just like they are a side effect of the CPU's wiring/design. There seems to be some patterns in what bits have to be set to get certain opcode and addressing mode, but they seem to be most consistent with ALU operations and there are a lot of exceptions as well.


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PostPosted: Thu Dec 27, 2018 3:40 am 
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https://github.com/eteran/pretendo/blob ... 2.txt#L820

"How" you implement your CPU core is up to you. There's truly nothing wrong with "a big case statement" for each opcode, but if you want to try and organise things by ALU or whatever else and invent some other model, go for it. CPU emulation is really not going to be your bottleneck, at least with regards to the above choices for opcode emulation; don't worry about it.

Edit: here's a chart organised by addressing mode/functionality... sort of. I don't find this intuitive at all, but YMMV: https://www.masswerk.at/6502/6502_instr ... tml#layout


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PostPosted: Mon Jan 07, 2019 1:00 am 
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A chart like that is useful, but according to a decode ROM from Atari (which was noted to be different from 6502's decode ROM) there are also cases in instruction decoding where certain bits are ignored rather than having to be 1 or 0. This as far as know wasn't illustrated in the chart. It might be possible to figure out most of the decode ROM from what is known about the instructions and their similarities and the "patterns" in the opcode table


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