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PostPosted: Mon Jun 03, 2019 1:02 am 
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I have PPU working mostly by accident but can't fully explain it so I would like to know more about background rendering. I've read and re-read wiki on PPU rendering but still have questions, like it states that there are 2x 16 bit registers. My guess is that one is for plane0 and one for plane1. Then each tile has 2bits giving access to 8pixels for rendering?

Then Wiki states "Every 8 cycles, the bitmap data for the next tile is loaded into the upper 8 bits of this shift register. Meanwhile, the pixel to render is fetched from one of the lower 8 bits." now this doesn't make sense then as 8bits only fit 4 tiles(2bits/tile), same goes for rendering however that would mean that fineX can't be more than 3. Can anyone shed some more light on this?


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PostPosted: Mon Jun 03, 2019 4:19 am 
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So it finally clicked for me it was just unfortunate timing to create this thread after a long time of digging into PPU.
So from my understanding there are 2x16bit registers and those 2 are for both planes of pattern, Plane0 and Plane1, so each register contains just 1 bit of each, making 16pixels in total, now as fineX is 3bits in size with a maximum value of 7 it means that we must be able to access 8 pixels at a time and PPU WIKI states that the low bits are fetched while the low ones are rendered while high bits are fetched and each fetch cycle they are shifted. I kinda believe this part could be clarified a a bit more clearly in the WIKI though. Now everything checks out, my PPU fine scrolling works and all the numbers add up


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PostPosted: Mon Jun 03, 2019 4:30 am 
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LukasP wrote:
I've read and re-read wiki on PPU rendering but still have questions, like it states that there are 2x 16 bit registers. My guess is that one is for plane0 and one for plane1. Then each tile has 2bits giving access to 8pixels for rendering?

2x 16 bits is 16 pixels, no?

Quote:
now this doesn't make sense then as 8bits only fit 4 tiles(2bits/tile)

That's probably why there are 2 registers.

I'm no expert on the internals of the PPU (I code NES programs, not emulators), but the wiki description makes perfect sense to me. I imagine something like this when reading that description:

Code:
Plane 0 FEDCBA98 76543210
Plane 1 FEDCBA98 76543210
        +------+ ^^^^^^^^
          load    sample
          area     area

And the fine X scroll dictates which position of the lower 8 is sampled for rendering.


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PostPosted: Mon Jun 03, 2019 7:08 am 
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Thanks @tokumaru for additional insight however that only makes sense once you've already glued the things together, like for example I must know from another wiki page that background tiles consist from 2 planes which is fine and I've already implemented it now, however it could be at least a mention in the PPU RENDERING page as well. It's hard to glue all the little details together when doing it for the first time from all the PPU pages, but now as I know that I will be able to tell others that it's pretty straight forward once such a question will arise ;)


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PostPosted: Mon Jun 03, 2019 9:28 am 
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I didn't even go to the wiki though, I was just using the information you included in your first post (which apparently comes from different pages), so I guess it's possible that the complete picture is not so easy to see.


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