DMC LFSR formula

Discuss emulation of the Nintendo Entertainment System and Famicom.

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johnmph
Posts: 12
Joined: Fri Feb 28, 2020 8:17 am

DMC LFSR formula

Post by johnmph » Sun Apr 05, 2020 8:42 am

Hello, I made some tests with Visual2A03 for the APU DMC and here is what I found for the LFSR :

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https://www.qmtpro.com/~nes/chipimages/visual2a03/?a=0&d=EA4C0000&a=fffc&d=0&a=fffd&d=0&logmore=pcm_bits,pcm_sr,pcm_freq,pcm_t

cycle	ab	db	rw	Fetch	pc	pcm_bits	pcm_sr	pcm_freq	pcm_t
-------------------------------------------------------------------------------------------------
0	00ff	00	1		00ff	0		ff	0		000	; Freq is $0 (Rate index 0), Shift register is $FF, LFSR is $0 !, Shifted bits counter is 0
0	00ff	00	1		00ff	0		ff	0		000
1	00ff	00	1	BRK	00ff	0		ff	0		000
1	00ff	00	1	BRK	00ff	0		ff	0		000
2	00ff	00	1		00ff	0		ff	0		001	; LFSR is $1 after shifted from $0
2	00ff	00	1		00ff	0		ff	0		001
3	01c0	00	1		00ff	0		ff	0		001
3	01c0	00	1		00ff	0		ff	0		001
...
1021	0002	00	1		0002	0		ff	0		080
1021	0002	00	1		0002	0		ff	0		080
1022	0003	00	1		0003	0		ff	0		100
1022	0003	00	1		0003	0		ff	0		100
1023	0000	ea	1	NOP	0000	1		7f	0		100	; First shift register clock after 1024 CPU cycles
1023	0000	ea	1	NOP	0000	1		7f	0		100
1024	0001	4c	1		0001	1		7f	0		19d	; LFSR is $19d after shifted from $100
1024	0001	4c	1		0001	1		7f	0		19d
...
1448	0000	ea	1	NOP	0000	1		7f	0		080
1448	0000	ea	1	NOP	0000	1		7f	0		080
1449	0001	4c	1		0001	1		7f	0		080
1449	0001	4c	1		0001	1		7f	0		080
1450	0001	4c	1	JMP Abs	0001	1		7f	0		100
1450	0001	4c	1	JMP Abs	0001	1		7f	0		100
1451	0002	00	1		0002	2		3f	0		100	; Second shift register clock after 1024 + 428 CPU cycles
1451	0002	00	1		0002	2		3f	0		100
Progression of pcm_t :

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000 = 0000 0000 0000 0000
001 = 0000 0000 0000 0001 | 1
002 = 0000 0000 0000 0010 << 1
004 = 0000 0000 0000 0100 << 1
008 = 0000 0000 0000 1000 << 1
010 = 0000 0000 0001 0000 << 1
021 = 0000 0000 0010 0001 << 1 | 1
042 = 0000 0000 0100 0010 << 1
084 = 0000 0000 1000 0100 << 1
108 = 0000 0001 0000 1000 << 1
011 = 0000 0000 0001 0001 << 1 | 1 & 1FF
023 = 0000 0000 0010 0011 << 1 | 1
046 = 0000 0000 0100 0110 << 1
08C = 0000 0000 1000 1100 << 1
118 = 0000 0001 0001 1000 << 1
030 = 0000 0000 0011 0000 << 1 & 1FF
061 = 0000 0000 0110 0001 << 1 | 1
0C2 = 0000 0000 1100 0010 << 1
184 = 0000 0001 1000 0100 << 1
109 = 0000 0001 0000 1001 << 1 | 1 & 1FF
013 = 0000 0000 0001 0011 << 1 | 1 & 1FF
027 = 0000 0000 0010 0111 << 1 | 1
04E = 0000 0000 0100 1110 << 1
09C = 0000 0000 1001 1100 << 1
139 = 0000 0001 0011 1001 << 1 | 1
072 = 0000 0000 0111 0010 << 1 & 1FF
0E5 = 0000 0000 1110 0101 << 1 | 1
...

Conclusion :

- Always shifted left by 1 bit
- 9 bits shift register
- Injected bit is : bit 8 XOR bit 4
Example of code to generate DMC LFSR for 3 clocks :

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int main(int argc, const char * argv[]) {
    
    // Need to find other values, just checked first rate
    uint8_t rates[] = { 0x9D };
    
    // Power-up with 0
    uint16_t lfsr = 0;
    
    // Power-up with 0
    uint8_t freq = 0;
    
    // Loop for 2 shift register clocks, the LFSR is clocked each 2 CPU cycles
    for (int cpuCycles = 2, clockCounter = 0; clockCounter < 3; cpuCycles+=2) {
        std::cout << std::dec << +cpuCycles << " : " << std::hex << +lfsr << "\n";
        
        // Check for clock
        if (lfsr == 0x100) {
            // Reload
            lfsr |= rates[freq];
            
            ++clockCounter;
            
            std::cout << "Clock\n";
            
            continue;
        }
        
        // Special case for starting at 0
        if (lfsr == 0x0) {
            // Load with 1
            lfsr = 0x1;
            
            continue;
        }
        
        // Xor on bit 4 and 8
        bool bit = ((lfsr & 0x100) != 0) ^ ((lfsr & 0x10) != 0);
        
        // Shift left by one bit, inject calculated bit and don't overflow
        lfsr = ((lfsr << 1) | bit) & 0x1FF;
    }
    
    return 0;
}
I don't know if somebody has already posted on this before, I made a small search and I found nothing on it, I don't know if it's very useful because the wiki provides already the correct period as CPU cycles but maybe this can interest somebody.

The interesting information is that the first shift register clock (after power-up) happen after 1024 CPU clocks.

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