VRC7 discoveries

Discuss emulation of the Nintendo Entertainment System and Famicom.

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SusiKette
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VRC7 discoveries

Post by SusiKette » Mon Feb 15, 2021 3:56 pm

I recently got back to inspecting the die shot of VRC7 and I found out few things that might be relevant to emulating the chip (or just in general interesting observations). I don't think any of these are mentioned on the wiki page either (or anywhere else as far as I have read).

While VRC7's master clock runs at 3.58 MHz, the chip has an internal clock divider that divides the master clock rate by 4, resulting to an internal clock rate of 0.895 MHz

Writing to $9010 or $9030 (when address is $00-$0F) takes approximately 8 master clock cycles. First few pass transistors in the write singal buffer are controlled by the master clock (and only ones on the chip), probably to make sure it can latch the write signal (which is generated by certain CPU address bits) by begin faster than the CPU itself. The buffered write signal activates after 4 master cycles and deactivates after 4 more master cycles. Now the write is completed.

$9030 writes to addresses $10-$35 are written the same way, but they are written to a data buffer. The reason is that these registers are contained in a shift registers. Only one slot is writable, so the buffer has a counter to keep track of the shift register slot in the writable position. When the counter value matches the relevant address bits from the latched address, the write is passed to the shift register. This is probably the reason why it is common to wait after every write. The actual wait time you need to wait depends on where the shift registers is at the time, but since it is impossible to know it is good idea to wait the longest required time. The shift register itself is advanced every internal clock cycle. And since there are 9 slots (leftover from original chip), it takes 9 * 4 = 36 master clock cycles for the shift registers to go through all slots.

By the way, where does the 42 CPU cycles (mentioned on the wiki page) of register write delay come from? Did someone time it or get it from a game that used this chip?

Also, how would you go about calculating how many CPU cycles some operations on VRC7 take? I would like to calculate more accurate times for different operations (especially the write times), but I'm not sure what kind of formulas/equations I need to calculate them.
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lidnariq
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Re: VRC7 discoveries

Post by lidnariq » Mon Feb 15, 2021 4:09 pm

SusiKette wrote:
Mon Feb 15, 2021 3:56 pm
By the way, where does the 42 CPU cycles of register write delay come from? Did someone time it or get it from a game that used this chip?
The official YM2413 datasheet claims 84 master clock cycles. Since the VRC7 runs at twice the 2A03 CPU clock ... 42.

Lagrange Point waits 59cy.

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SusiKette
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Re: VRC7 discoveries

Post by SusiKette » Mon Feb 15, 2021 5:25 pm

lidnariq wrote:
Mon Feb 15, 2021 4:09 pm
The official YM2413 datasheet claims 84 master clock cycles. Since the VRC7 runs at twice the 2A03 CPU clock ... 42.
Oh? I have only seen a datasheet of YM2413 where the only thing given in cycles is the reset pulse width. Do you know where to find this datasheet that list this info?

Also, according to my current understanding of the write timings you would only need wait 22 CPU cycles between writes (or maybe a few more to be safe). Since buffering the write signal takes 8 master cycles and 36 master clock cycles for the shift register to go through all the slots. This should be enough time for the shift register access buffer to put the buffered data in the shift register. I can't yet say for 100% certainty if that's correct. Maybe the best way is for someone to test this on real VRC7.
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lidnariq
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Re: VRC7 discoveries

Post by lidnariq » Mon Feb 15, 2021 5:47 pm


NewRisingSun
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Re: VRC7 discoveries

Post by NewRisingSun » Mon Feb 15, 2021 5:51 pm

Yes, most of the Yamaha FM chips have a very brief "data sheet" and a more detailed "application note". The necessary delays are usually only included in the latter.

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rainwarrior
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Re: VRC7 discoveries

Post by rainwarrior » Mon Feb 15, 2021 5:53 pm

Page 4 of this one:
https://www.datasheetarchive.com/pdf/do ... 191&type=M
It states 12cy after address, 84cy after data.

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Re: VRC7 discoveries

Post by Pokun » Tue Feb 16, 2021 1:34 pm

I remember reading about a mistake in the original YM2413 application manual. Don't know if SMS power got it corrected. Here it is.

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Ben Boldt
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Re: VRC7 discoveries

Post by Ben Boldt » Thu Feb 18, 2021 2:48 pm

Do you see any possible detection of register $9008 on the VRC7 die?

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SusiKette
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Re: VRC7 discoveries

Post by SusiKette » Thu Feb 18, 2021 3:13 pm

Ben Boldt wrote:
Thu Feb 18, 2021 2:48 pm
Do you see any possible detection of register $9008 on the VRC7 die?
I have checked the address decoder already, but I might need some elaboration on what you mean.
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lidnariq
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Re: VRC7 discoveries

Post by lidnariq » Thu Feb 18, 2021 3:14 pm

$9008/$9010 selects the YM2413.

All sixteen addresses (A14, A13, A12, A3-or-A4) are decoded: https://siliconpr0n.org/map/konami/vrc_ ... y=1179&z=6

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Ben Boldt
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Re: VRC7 discoveries

Post by Ben Boldt » Thu Feb 18, 2021 3:24 pm

Sorry I got mixed up, I thought I remembered an address suspiciously missing but I may have been thinking of a different mapper. When I posted that, I quickly scanned the wiki for one that looked missing, I spotted $9008 but I now realize the xxx8/xx10 are just board variations... And the board that does xxx8 doesn't support audio so $9008 isn't listed. Sorry for the convoluted explanation, never mind my original question.

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Re: VRC7 discoveries

Post by tepples » Thu Feb 18, 2021 6:14 pm

I'm in contact with SMS Power staff. What change do I need to pass on?

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SusiKette
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Re: VRC7 discoveries

Post by SusiKette » Sun Feb 21, 2021 10:36 am

I took a look at the timing logic and I realized that the counter that keeps track of the shift register position actually only resets every 18 cycles instead of 9 cycles like I originally thought. The timing sequence itself is 18 cycles long. The shift register is writable only on the first 9 cycles (or 6 to be specific on the VRC7's case). So if my new calculations are correct it actually takes up to 80 master cycles to handle the write. The 4 extra cycles that were added to the application manual probably were added to be safe. The mistake I made was mainly caused because I didn't know how the timing logic worked at the time, so I didn't know when and how often the counter was reset.

Next I'll be trying to figure out how VCR7 disables the 7, 8 and 9 channels. The chip does seem to support all 9 channels, so they must have been disabled some way other than completely removing them from the circuit.

I will also take a look at if the rhythm mode itself is functional. Right now it seems like that you need to enable debug mode to enable it (otherwise the signal is forced low regardless of the value stored in the register), but I'm not sure if it was disabled elsewhere too so it can't be used.
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Re: VRC7 discoveries

Post by rainwarrior » Sun Feb 21, 2021 10:55 am

SusiKette wrote:
Sun Feb 21, 2021 10:36 am
The 4 extra cycles that were added to the application manual probably were added to be safe.
I dunno if it's common to do this in applications of the YM2413, but at least on the Famicom the VRC7 runs on its own clock that's less precise (3 sig figs?) than the Famicom's clock. Even though it's nominally a multiple of the frequency they didn't tie it together, so I think they definitely need some room for slop there.

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