PPU PT shift registers q.

Discuss emulation of the Nintendo Entertainment System and Famicom.

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Anes
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PPU PT shift registers q.

Post by Anes » Fri Jun 10, 2005 2:59 am

Reading what it says 2C02 reference, it says that "while pt data is fetched is loaded into internal latches" then there are 2 - 16 bit shift registers where the latched are copied at the upper 8 bits, and both shift reg. shift *right* every clock cycle (first 256 of course), but i dont know if i missunderstanding something or the doc is not right, cos how can be "right shift"?, assuming that FineX is always set to 0 (not scrolling) if we shift right one time per cycle and get the bit according FineX this will result in reversing the tiles while we render, what acctually happens in my emulator, after i changed my pseudo-by-pixel engine to a NES hardware behaivor.

Some help?
ANes

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Disch
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Post by Disch » Fri Jun 10, 2005 7:27 am

Might be a typo. High bit represents the first pixel, so left shifting does make more sense.

*shurg*

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