Phase 161 through 168

Discuss emulation of the Nintendo Entertainment System and Famicom.

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Anes
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Phase 161 through 168

Post by Anes » Sun Jun 12, 2005 8:23 pm

My question is about when the ppu fetches the first 2 tiles to be rendered
at the beggining of the scanline, cos i have been having problems with it in my emulator.

First i want to know if what i "know" is right:

- The ppu fetches two NT bytes (1 tile) every 8 clock cycles
- The first tile fetched is the 3rd to be drawn on screen
- cycles that correspond to phase 161 - 168, repeats 2 times a tile fetch, so it fetch 2 tiles and those tiles will be drawn at the *next * scanline, prior the scanline that they were fetched.

But, if assumming that those 2 tiles fetched goes in the 1st and 2nd Tile it means that the ppu start to fectch tiles for the actual scanline from cc 16??? this is the point a dont understand, if we fetched two tiles at the begginning of the prior scanline it means it has to pass 16 cycles so it can start drawing tile 3rd.

Some help witch my confusion?
ANes

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Quietust
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Post by Quietust » Sun Jun 12, 2005 9:27 pm

The tile fetched at "cycles 0-3" of scanline N is the 3rd one to be drawn on scanline N.
The tiles fetched at "cycles 160-167" of scanline N-1 are the 1st and 2nd ones drawn on scanline N.

The reason the first two tiles are fetched in advance is to prefill the shift register used by the renderer itself; 1 tile is not enough, since it needs 15 pixels ready if fine X scroll is equal to 7. The fact that the PPU ends up fetching 34 tiles per scanline (instead of only 33 as required) is just a side effect of simplifying the logic.
Quietust, QMT Productions
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Anes
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Post by Anes » Mon Jun 13, 2005 10:04 am

so every "tile fetch" is every 4 clock cycles?
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tepples
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Post by tepples » Mon Jun 13, 2005 7:26 pm

Correct, provided that your timing is based on PPU memory cycles. Most of the PPU logic actually runs at one cycle per pixel, but the address and data buses are multiplexed onto one set of pins, so one PPU memory cycle happens every two pixels. There are eight pixels in a tile. Therefore, the PPU reads VRAM or VROM four times to draw one tile:
  1. Nametable
  2. Attribute table
  3. Pattern table low order bits
  4. Pattern table high order bits

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