Sweet finding w/ VBlank

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Zepper
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Sweet finding w/ VBlank

Post by Zepper » Sat Feb 09, 2008 8:27 pm

8) Reading 1 PPU clock before VBL should suppress setting

- My emulator has used an hack for this "special case". However, verifying a cycle counter when equals to 1 looks incorrect, so here's a sweet finding:

"The PPU executes 3 cycles for each CPU clock [NTSC]. If the VBlank flag rises at cycle 341 (the 3rd cycle), it takes effect on the next PPU clock".

Code: Select all

PPU scanline cycle
0 1 2 3... 338, 339, 340 [line 240]
......................^ VBL (2002h:7 reads 0)

0 1 2 3... 338, 339, 340 [line 241]
^ VBL (2002h:7 reads 1)
- I traced the CPU/PPU and $2002:7 had been suppressed. In other words, if VBlank starts during the 2nd or 3rd byte of a LDA $2002, then the VBlank flag rises on the next instruction, so reading 2002h (lda) returns bit 7 as clear; it might be much like the hardware thing.

- Of course that such behavior implies the same (may) occurs with the VBlank flag clearing. ;)
Last edited by Zepper on Fri Feb 19, 2010 7:22 am, edited 4 times in total.

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