Problem with indirect indexed addressing timing (nestest)

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HastatusXXI
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Joined: Sat Aug 25, 2018 7:21 am

Problem with indirect indexed addressing timing (nestest)

Post by HastatusXXI » Wed Aug 29, 2018 11:33 am

Hello.
I've made some progress with my 6502 emulator and it runs nestest like a charm, except for the PPU dots. I'm trying to adjust the timing of the instructions (taking into account 1 CPU cycle = 3 dots). I have a problem with this instruction:

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DB65  91 33     STA ($33),Y = 0400 @ 0400 = 7F  A:87 X:06 Y:00 P:E5 SP:FB CYC:239
DB67  AD 00 04  LDA $0400 = 87                  A:87 X:06 Y:00 P:E5 SP:FB CYC:257
The problem here is the log shows the STA instruction should take 6 cycles. However, STA only takes 6 cycles when page boundary is crossed : http://atarihq.com/danb/files/64doc.txt

Code: Select all

 Indirect indexed addressing

     Read instructions (LDA, EOR, AND, ORA, ADC, SBC, CMP)

        #    address   R/W description
       --- ----------- --- ------------------------------------------
        1      PC       R  fetch opcode, increment PC
        2      PC       R  fetch pointer address, increment PC
        3    pointer    R  fetch effective address low
        4   pointer+1   R  fetch effective address high,
                           add Y to low byte of effective address
        5   address+Y*  R  read from effective address,
                           fix high byte of effective address
        6+  address+Y   R  read from effective address

       Notes: The effective address is always fetched from zero page,
              i.e. the zero page boundary crossing is not handled.

              * The high byte of the effective address may be invalid
                at this time, i.e. it may be smaller by $100.

              + This cycle will be executed only if the effective address
                was invalid during cycle #5, i.e. page boundary was crossed.
There isn't page boundary crossing this time (since Y = 0). So, why does the log state the instruction should take 6 CPU cycles?

lidnariq
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Re: Problem with indirect indexed addressing timing (nestest

Post by lidnariq » Wed Aug 29, 2018 11:44 am

HastatusXXI wrote:STA
Read instructions (LDA, EOR, AND, ORA, ADC, SBC, CMP)
STA does its own thing. (It always reserves the extra cycle regardless of whether there's carry-out)

HastatusXXI
Posts: 40
Joined: Sat Aug 25, 2018 7:21 am

Re: Problem with indirect indexed addressing timing (nestest

Post by HastatusXXI » Wed Aug 29, 2018 11:49 am

lidnariq wrote:
HastatusXXI wrote:STA
Read instructions (LDA, EOR, AND, ORA, ADC, SBC, CMP)
STA does its own thing. (It always reserves the extra cycle regardless of whether there's carry-out)
Ok, it's specified here, just as you say: http://atarihq.com/danb/files/64doc.txt

I didn't notice that detail in the documentation. Thank you!

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Quietust
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Re: Problem with indirect indexed addressing timing (nestest

Post by Quietust » Fri Aug 31, 2018 6:37 am

In case you want to know why STA is different: with the various Read instructions, it's "okay" to read from the wrong address on the first cycle and then read from the correct address on the second cycle if necessary, but writing to the wrong address is totally unacceptable, so it always does a dummy read from the unadjusted (and possibly correct) address before doing the actual write.

Note that this means that writing to an I/O register using indirect indexed addressing is probably a bad idea, since it will also read from it immediately beforehand; if, however, you actually need to read from an I/O register immediately before writing it, this would be a good way of doing it (though it would require sacrificing 2 bytes of zero page for a minor speed boost, which may be of questionable benefit).
Quietust, QMT Productions
P.S. If you don't get this note, let me know and I'll write you another.

HastatusXXI
Posts: 40
Joined: Sat Aug 25, 2018 7:21 am

Re: Problem with indirect indexed addressing timing (nestest

Post by HastatusXXI » Fri Aug 31, 2018 8:56 am

Ok, thank you for the clarification on STA, Quietust!

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