It is currently Wed Oct 18, 2017 2:15 am

All times are UTC - 7 hours





Post new topic Reply to topic  [ 1 post ] 
Author Message
 Post subject: Sweet finding w/ VBlank
PostPosted: Sat Feb 09, 2008 8:27 pm 
Offline
Formerly Fx3
User avatar

Joined: Fri Nov 12, 2004 4:59 pm
Posts: 3064
Location: Brazil
8) Reading 1 PPU clock before VBL should suppress setting

- My emulator has used an hack for this "special case". However, verifying a cycle counter when equals to 1 looks incorrect, so here's a sweet finding:

"The PPU executes 3 cycles for each CPU clock [NTSC]. If the VBlank flag rises at cycle 341 (the 3rd cycle), it takes effect on the next PPU clock".

Code:
PPU scanline cycle
0 1 2 3... 338, 339, 340 [line 240]
......................^ VBL (2002h:7 reads 0)

0 1 2 3... 338, 339, 340 [line 241]
^ VBL (2002h:7 reads 1)


- I traced the CPU/PPU and $2002:7 had been suppressed. In other words, if VBlank starts during the 2nd or 3rd byte of a LDA $2002, then the VBlank flag rises on the next instruction, so reading 2002h (lda) returns bit 7 as clear; it might be much like the hardware thing.

- Of course that such behavior implies the same (may) occurs with the VBlank flag clearing. ;)

_________________
Zepper
RockNES developer


Last edited by Zepper on Fri Feb 19, 2010 7:22 am, edited 4 times in total.

Top
 Profile  
 
Display posts from previous:  Sort by  
Post new topic Reply to topic  [ 1 post ] 

All times are UTC - 7 hours


Who is online

Users browsing this forum: No registered users and 4 guests


You cannot post new topics in this forum
You cannot reply to topics in this forum
You cannot edit your posts in this forum
You cannot delete your posts in this forum
You cannot post attachments in this forum

Search for:
Jump to:  
Powered by phpBB® Forum Software © phpBB Group