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PostPosted: Tue Aug 05, 2008 3:13 pm 
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Joined: Tue Jun 17, 2008 11:51 am
Posts: 61
Hello, I am having some trouble passing the test. I use cycle by cycle rendering based on nintendulator which for every memory access I do a PPU run for 3 cycles and then do the operation. I ran into trouble with test 4, the Vblank clear timing test. I am getting Error number 4 - Cleared one PPU clock too early. If I edit the memory reg2002 code to something like
if (Ppu.Scanline == 241 && Ppu.Ccycle == 0) return tmp & ~0x80;
This solves the problem for the PPU test number 2. However if I set the conditional Ppu.Ccycle == 1, this allows me to pass test 4 and but fail test 2 and 3. In the wiki it says vblank is cleared after 20 scanlines, which I seem to do properly, every 6820 cycles. How do I fix this?


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