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PostPosted: Sun Jul 24, 2005 8:08 pm 
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from Kevtris' pages:

http://www.tripoint.org/kevtris/mappers ... R1ROM.html
http://www.tripoint.org/kevtris/mappers ... TVROM.html

I'm trying to understand the specifics. What I know:

- These boards have only 4k usable RAM (presumably accessed via $6000-$6FFF).
- $7xxx mirrors $6xxx (A12 pulled low)
- despite only 4k of RAM being accessable, 8k of RAM exists on the board


What I am unsure about:

- I know at least the two extra nametables for the 4-screen mirroring come from cartridge RAM. But do all 4 nametables use cartridge RAM (leaving the PPUs internal nametables unused)?

- It makes sense that the nametables would exist on the unused area of RAM ($7800-$7FFF -- or $7000-$7FFF if all 4 nametables). But is that the case? Or do they exist at the same RAM accessed via $6xxx?
- If the above is the case, would it be possible to draw to the nametables by writing to $6xxx?


Anyway, any light shed on the situation would be appreciated ^^. I know this stuff isn't necessary for emulating Gauntlet and Rad Racer 2, but I'd like to know anyway. Thanks in advance.


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PostPosted: Sun Jul 24, 2005 8:33 pm 
Eh? The RAM is on the PPU bus, not the CPU bus. A12 of the RAM is tied low, yes, making it look like a 4 KB RAM instead of an 8 KB RAM (because RAMs come in leaps of 4 (add a row, add a column), so 2 KB, 8 KB, 32 KB, and so forth, other sizes are either more expensive (i.e. 16 KB), or non-existant), but it doesn't appear at any point in the CPU's memory map, only accessable via the PPU read/write port.

Since there aren't any extra IC's on there (nor is there any point to using both, unless they only provided 2 KB of RAM), the internal CIRAM is disabled, and the 8 KB RAM is mapped into PPU $2000+

Probable wiring map:
VCC -> CIRAM_/CE
GND or VCC -> CIRAM_A10 (doesn't really matter, does it, but not N/C)
PPU_NA13 -> 8KB_RAM_/CE
PPU_A10 -> 8KB_RAM_A10
PPU_A11 -> 8KB_RAM_A11
GND -> 8KB_RAM_A12


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PostPosted: Sun Jul 24, 2005 8:45 pm 
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Chalk this up to my lack of hardware understanding =P

Anyway, that clears it up. So no extra WRAM and the cartridge RAM is used for nametables only (only accessable via $2007).

Thanks a bunch.


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PostPosted: Sun Jul 24, 2005 8:49 pm 
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Putting VRAM into CPU$6000 would be cool, especially for "pseudo-bitmap" engines, but it would require a lot of latches to keep PPU reads from interfering with CPU writes, and these latches would need to be made of either a buttload of discrete chips or a CPLD.


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PostPosted: Sun Jul 24, 2005 9:23 pm 
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I figured it would be unlikely... but MMC5 has something similar going with ExRAM (it can be used as a nametable and still be written to via $5C00+) so I wasn't 100% sure.


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PostPosted: Sun Jul 24, 2005 9:27 pm 
MMC5's exwram is internal to the mapper though, and the mapper runs pretty much every NES line through it, so it can internally arbitrate between CPU and PPU (it's pretty much one way or another though iirc, either the cpu can write to it and the ppu can't see it, or the ppu can see it and the cpu can't touch it, until you switch modes).


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PostPosted: Sun Jul 24, 2005 9:40 pm 
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Don't ExRAM modes 0 and 1 allow for CPU writing and PPU reading? I think Just Breed writes to ExRAM without changing modes (uses mode 1) -- though granted it does it during VBlank. I specifically recall that dis-allowing CPU writes to ExRAM in modes 0 and 1 will break Just Breed (that's how I initially had it in my emu before reading below pasted section more carefully)

From http://tripoint.org/kevtris/mappers/incoming/mmc5.txt :

Quote:
* When in mode 0 or 1, the EXRAM is available for use by the PPU.

[snip]

* In modes 0 through 2, EXRAM is writable by the CPU at 5C00h-5FFFh


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PostPosted: Sun Jul 24, 2005 9:46 pm 
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Disch wrote:
Don't ExRAM modes 0 and 1 allow for CPU writing and PPU reading?

Correction: these latches would need to be made of either a buttload of discrete chips or a CPLD or an ASIC. MMC5 is such an ASIC. I left off "or an ASIC" because it's unlikely that the homebrew community could design and produce a custom ASIC.


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PostPosted: Sun Jul 24, 2005 9:49 pm 
I recalled wrong then. Humm, neat (but also painful, if I ever plan on getting MMC5 working in hardware). Is Just Breed a famicom game?

Actually, it might not be too bad (well, compared to how complicated MMC5 already is) if it's only allowed during V-blank, then you basically just map the VRAM back and forth automatically when the PPU state machine enters/leaves v-blank (and the MMC5 has to be watching that anyways) instead of being a totally manual setting.


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PostPosted: Mon Jul 25, 2005 1:36 am 
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Disch wrote:
Don't ExRAM modes 0 and 1 allow for CPU writing and PPU reading? I think Just Breed writes to ExRAM without changing modes (uses mode 1) -- though granted it does it during VBlank. I specifically recall that dis-allowing CPU writes to ExRAM in modes 0 and 1 will break Just Breed (that's how I initially had it in my emu before reading below pasted section more carefully)

Just Breed switches to mode 2 only while loading a screen, but it uses only mode 1 while scrooling and it writes to the ExRam only OUT of VBlank, else, only $00 would be written instead. It simply allows the game to have MUCH more time to write to the EXRAM and Just Breed uses it to move all the characters and the monsters, and also other battle stuff.
When loading a screen, scince redering is off trough $2001.4 and $2001.5, all writes to EXRAM will be only $00, so it must turn to mode 2, the other solution would be to turn the screen on but setup all palettes on solid black, so the player couldn't see anything.
Yeah, Just Breed is a famicom game, but also the best ever made.

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