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 Post subject: questions... apu & cpu
PostPosted: Wed Aug 10, 2005 2:35 pm 
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Formerly Fx3
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1. CPU
- I wonder about JSR or JMP instructions. If an IRQ/NMI is pending, can it be triggered right after a JSR or JMP?

2. APU
- By taking blargg's test 4 (clock jitter). My emu fails on test #3. I did a lot of debugging and I could find the reason: for some unknown way, the step 3 (0,1,2,3 mode #0) does NOT set the frameIRQ flag before a read to 4015, making the test #2 to be OK and test #3 to fail. The solution (a hack) is to check if the apu cycle counter has expired before a 4015h read - this way, the channel clock happens (on that specific cycle) & problem is fixed, but it's a hack, which I don't like to add it. I could get almost ALL the tests running OK with "hacks" to cycle counter. I'd like some advice... Tell me if unclear.

- When writting to 4017h, there's a statement about EVEN and ODD cycles. On ODD cycles, the quarter-step starts after 1 cycle, *and* mode #5 too, meaning TWO cycles of delay???

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PostPosted: Wed Aug 10, 2005 3:55 pm 
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Fx3 wrote:
1. CPU
- I wonder about JSR or JMP instructions. If an IRQ/NMI is pending, can it be triggered right after a JSR or JMP?


Sure, seems like it'd be the same as any other instruction in that regard. If not, a loop like "here: JMP here" would never be interrupted.


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PostPosted: Thu Aug 11, 2005 1:25 am 
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The IRQ flag is set on three consecutive clocks. In my timing notes I have it first set one clock before the fourth step, using timing where CPU reads and writes for a particular clock occur before other operations:

Code:
...
29829 Perform CPU read/write
      Set frame IRQ flag
29830 Perform CPU read/write (except special cases for length etc.)
      Set frame IRQ flag
      (other operations for fourth step)
29831 Perform CPU read/write
      Set frame IRQ flag
29832 Perform CPU read/write
...


As for the actual IRQ timing, all I could do was find out when it occurred, not exactly when the IRQ line is asserted and how the CPU timing works internally. So there might be more than one internal setup the test passes for, without guidance on which one is actually the case. Someone needs to study the Rockwell manual to figure out which clock of an instruction the IRQ line needs to be asserted at for it to occur before the next instruction. One thing I'm fairly sure of is that if the IRQ is asserted at the beginning of an instruction, that instruction will complete first.

I wish I had a better idea as to why the length counters exhibit their subtle behavior (delayed effect of halt flag, etc.). I'm really thinking that a simpler subset of the APU would be worth designing, since even the latest info I posted is a simplification.

Fx3 wrote:
When writting to 4017h, there's a statement about EVEN and ODD cycles. On ODD cycles, the quarter-step starts after 1 cycle, *and* mode #5 too, meaning TWO cycles of delay???


The timing listed in the new info shows timing when the write to $4017 is on an even internal APU clock (1.79 MHz source). When the write to $4017 is on an odd clock, add one to the timing tables. Put another way, a write to $4017 on an odd clock is treated as if it actually occurred one clock later (an even clock), with regard to timing of the new mode.


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 Post subject:
PostPosted: Thu Aug 11, 2005 10:58 am 
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Perhaps I'm not adding cycles on cpu reads/writes? I'm adding the amount of cycles for the current instruction. Yes, I use a cycle table for all instructions. This might be the problem here...

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