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 Post subject: quick stupid question
PostPosted: Mon Aug 15, 2005 3:43 pm 
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Formerly Fx3
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By taking STA $xxxx as example. It takes 4 cycles, right? Two cycles to fetch the address (low/high byte) and 2 more cycles to complete the instruction.

I'm asking this because I'm not "eating" CPU cycles on data read/write, so I'd like to fix this problem, that (supposely) makes the blargg's APU tests to fail here.

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PostPosted: Mon Aug 15, 2005 4:27 pm 
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4 cycles:

1) Read the opcode
2) Read low byte of address
3) Read high byte of address
4) Write A to address


http://nesdev.com/6502_cpu.txt

That doc has details on other addressing modes/instructions


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PostPosted: Mon Aug 15, 2005 5:50 pm 
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Fx3 wrote:
I'm asking this because I'm not "eating" CPU cycles on data read/write


Eh?

Quote:
I'd like to fix this problem, that (supposely) makes the blargg's APU tests to fail here.


I'm pretty sure the recent set of APU tests only use absolute addressing for accessing the APU, where the read/write occurs on the fourth (last) clock of the instruction. If you can provide information about which test is failing and the result code, post it to the APU test ROMs thread.


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PostPosted: Tue Aug 16, 2005 11:42 am 
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Well, 7457 cycles per quarter seems to fail. I'm using 7458 cycles and everything matches your document, blargg (I mean, the amount of cycles for first step, first clock etc.).

When I said "eating", I bet you understood it... ^_^;;

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