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PostPosted: Thu Oct 13, 2005 8:35 pm 
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Let's get power-up and reset behavior worked out. Add your ideas of things to test, preferably those related to emulation problems. Mention if you need a test ROM to test your emulator, otherwise I'll release a batch of test ROMs later.

I didn't find any APU unavailability at power-up or reset. The squares, triangle, noise, and DMC all worked immediately. The frame counter mode could be changed and $4015 reported length counter status properly.

I tested the PPU's VBL flag. It's set at power-up and cleared at reset, and next set about 27384 clocks later.


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PostPosted: Thu Oct 13, 2005 8:43 pm 
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edit - er... maybe I should actually read your post.

with a little simple math it looks like it's starting at the end of the pre-render scanline: 27384 * 3 / 341 = ~240.9 scanlines between flag sets... that covers all rendered scanlines and the dummy scanline afterward

VBlank flag is cleared on reset? Does anyone have the Cobra Triangle cart? would it ever deadlock on soft-reset? If it waits 2 full frames before changing apu frame modes... that APU frame IRQ is going to hit and the game will lock up as soon as you start. Unless there's something we're missing....


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PostPosted: Thu Oct 13, 2005 9:43 pm 
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Here's a quick breakdown of Cobra Triangle from my tracer:

Code:
PC     Binary      Inst                       A   X   Y   [NVIZC]  SP
=====================================================================
FF90   78          SEI                       00  00  00   [..IZ.]  FD
FF91   A9 00       LDA  #$00                 00  00  00   [..IZ.]  FD
FF93   8D 00 80    STA  $8000    [8000=6C]   00  00  00   [..IZ.]  FD
FF96   4C 1E 80    JMP  $801E    [801E=78]   00  00  00   [..IZ.]  FD
801E   78          SEI                       00  00  00   [..IZ.]  FD
801F   D8          CLD                       00  00  00   [..IZ.]  FD
8020   A2 FF       LDX  #$FF                 00  FF  00   [N.I..]  FD
8022   9A          TXS                       00  FF  00   [N.I..]  FF
8023   A9 10       LDA  #$10                 10  FF  00   [..I..]  FF
8025   8D 00 20    STA  $2000    [2000=FF]   10  FF  00   [..I..]  FF
8028   20 F9 82    JSR  $82F9    [82F9=AD]   10  FF  00   [..I..]  FD
82F9   AD 02 20    LDA  $2002    [2002=FF]   80  FF  00   [N.I..]  FD  <--- first wait for VBlank loop
82FC   10 FB       BPL  $FB      [82F9=AD]   80  FF  00   [N.I..]  FD
82FE   60          RTS                       80  FF  00   [N.I..]  FF
802B   20 F9 82    JSR  $82F9    [82F9=AD]   80  FF  00   [N.I..]  FD
82F9   AD 02 20    LDA  $2002    [2002=FF]   00  FF  00   [..IZ.]  FD  <--- second wait for VBlank loop
82FC   10 FB       BPL  $FB      [82F9=AD]   00  FF  00   [..IZ.]  FD
[snip]
82F9   AD 02 20    LDA  $2002    [2002=FF]   80  FF  00   [N.I..]  FD
82FC   10 FB       BPL  $FB      [82F9=AD]   80  FF  00   [N.I..]  FD
82FE   60          RTS                       80  FF  00   [N.I..]  FF
802E   20 3D 81    JSR  $813D    [813D=A9]   80  FF  00   [N.I..]  FD
813D   A9 00       LDA  #$00                 00  FF  00   [..IZ.]  FD
813F   A2 17       LDX  #$17                 00  17  00   [..I..]  FD
8141   9D 00 40    STA  $4000,X  [4017=FF]   00  17  00   [..I..]  FD   <-- reset frame mode here (still mode 0)
8144   CA          DEX                       00  16  00   [..I..]  FD
8145   10 FA       BPL  $FA      [8141=9D]   00  16  00   [..I..]  FD
[snip -- clears $4016 and all sound regs here]
8141   9D 00 40    STA  $4000,X  [4000=FF]   00  00  00   [..IZ.]  FD
8144   CA          DEX                       00  FF  00   [N.I..]  FD
8145   10 FA       BPL  $FA      [8141=9D]   00  FF  00   [N.I..]  FD
8147   A9 C0       LDA  #$C0                 C0  FF  00   [N.I..]  FD
8149   8D 10 40    STA  $4010    [4010=FF]   C0  FF  00   [N.I..]  FD
814C   A9 80       LDA  #$80                 80  FF  00   [N.I..]  FD
814E   8D 17 40    STA  $4017    [4017=FF]   80  FF  00   [N.I..]  FD   <-- change frame mode here (note, frame IRQs not disabled, just mode changed)

Note again that Frame IRQs are NEVER disabled OR Acknowledged... so if a Frame IRQ trips after reset and before the first $4015 write, the game
is screwed and will lock up as soon as it CLIs.


If that first wait-for-vblank loop actually takes a full frame, the game will be stalled for two frames before it changes modes -- which is more than enough time for a frame IRQ to fire, screwing the ROM in the rear. If soft resetting starts emulation just after VBlank and with $2002.7 clear... I don't see how it's not deadlocking on the real system.. not unless there's something we're missing (is there another way to acknowlege Frame IRQs?)


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PostPosted: Thu Oct 13, 2005 10:38 pm 
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I just tested and on reset it is as if $4017 were rewritten with the last value written, not $00. That is, the current frame mode is restarted and the current frame IRQ inhibit is unchanged (the current frame IRQ flag, on the other hand, is cleared). So once Cobra Triangle has configured the APU mode, it won't change when you reset.


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PostPosted: Thu Oct 13, 2005 10:59 pm 
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Excellent.

I suppose it would still be theoretically possible to lock the game up by pressing reset between those two $4017 writes (but you'd have to be pretty quick!). I'll chalk this up to sloppy coding on their part. But hey... I guess it worked.

That's good to know about the $4017 on reset thing. That combined with $2002.7 being high immediately after powerup clears up a lot of my confusion/problems.

So... to recap... lemme make sure my understanding is right:

- Execution starts on or near the very end of the pre-render scanline.. on both powerup and reset
- $2002.7 is high on powerup, but low on reset
- last value written to $4017 is echoed to $4017 ~10 cycles before reset.. whereas $00 is fed to $4017 ~10 cycles before powerup
- a pending APU frame IRQ is cleared on reset (and I guess you could say on powerup as well)


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PostPosted: Fri Oct 14, 2005 1:09 am 
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Quote:
- Execution starts on or near the very end of the pre-render scanline.. on both powerup and reset


That sounds like a reasonable interpretation. Once I gather more data it'll be clearer. Some of the PPU registers don't function for the first frame or so. Maybe it's not even doing scanlines at first (what matters most is how this affects the CPU).

Quote:
- last value written to $4017 is echoed to $4017 ~10 cycles before reset.. whereas $00 is fed to $4017 ~10 cycles before powerup
- a pending APU frame IRQ is cleared on reset (and I guess you could say on powerup as well)


Exactly.

Hmmm, I just tested $2002.7 with different power-down intervals between and it was often 0 at power-up. Also about 1 out of 20 resets it was also set. The time it next gets set seems consistent, though. I tested when it is naturally cleared and found that at about 29659, but nothing before that. I only checked at 1000, 2000, 3000, 4000, 5000, 10000, 15000, 20000, and 25000 clocks after power-up. So it's set around 27384 and cleared around 29659, which is close enough to the standard VBL length.

My NES development folder needs a big cleanup. I've got almost a thousand asm files for various tests and stuff. I'm finally getting a good scheme set up, where I have reverse-engineering/apu/frame_irq/ with several asm files in it, each demonstrating a particular behavior. Then I have reverse-engineering/apu/summary.txt with a summary of the findings of each test in a format like you've used above. Then of course I've got validation/apu/ with the emulator test ROMs. I don't know why it's taken so long to figure this organization out. Still leaves hundreds of individual source files.


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