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PostPosted: Sat Nov 13, 2010 6:15 pm 
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jwdonal wrote:
That's really cool. I'm not even close to where you are. Is this all still fitting in the Cyclone I with ~12K LEs? Or have you moved to a larger device? It's hard for me to compare Altera devices resource wise to Xilinx (which is what I'm using) since Altera vs. Xilinx resource terminology is very different. It looks like on your new board the Cyclone chip is a bit bigger this time around - did you move up to a Cyclone II instead? Also, (and yes I realize this may be considered NDA/proprietary/secret so I don't actually expect an answer to this, lol) what current resource utilization are you at within the cyclone with the entire CPU+PPU+APU+mappers+etc? 25%, 50%, 75%, 90%?

So from you've said it appears you've moved away from the original PIC microcontroller and replaced it with this Vinculum 2 instead. PIC is certainly very popular whereas I've never heard of the Vinculum before. PIC also has good IDE tools and lots of freely availble IP. Why did you switch away from the PIC? Was there something that you just really didn't like about it?

Also, I sent you a PM regarding a very specific CPU design question. I didn't post it here because it doesn't relate at all to this topic and don't want to get things off-track. Mind taking a peak?

Pz!

Jonathon :)


Sure I can tell ya. Right now I am using a cyclone 3 25K model, same size chip (240 pins) as the previous model, but 2x more gate-age.

It is using 65% of the device for everything, and I expect it to hit 70% when I finish the vinculum interface stuff to do system control.

It does not fit on the old FPGA any more, but it could easily be trimmed to fit if needed, though I have finished with that old hardware now and won't use it again probably.

I selected altera, because xilinx's programming environment is a huge steaming pile of poo. Buggier than a swamp in june, in #nesdev I watched people struggle with it; compiles that work but then the device doesn't, unless they downgrade the compiler.

the entire design is all verilog now, with a single top level schematic just linking 6 or so verilog top modules together (CPU, PPU, mappers, audio, video, controllers, SDRAM). All of the hardware-specific pieces are cordoned off in a single verilog "Technology" file as I called it, mainly the blockrams. This was in case the design needs to be ported, it should be possible to just replace this 1 file and it can work on another vendor's parts.

As memblers said, I changed from PIC to vinculum because I wanted 2 USB ports on it for controllers. So far I have had problems just getting the damn thing to compile and work but I got all that solved and the chip is happily lighting the segments of the LED display up in a cylon-like pattern. At this point I am going to write all the basic hardware interface doohickeys and go from there.

This vinculum chip is fairly cheap, too.

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PostPosted: Sun Nov 14, 2010 3:07 am 
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Hi All,

I really like to see the same thing happened as 1chipMSX on NES/FC.
http://en.wikipedia.org/wiki/1chipMSX
I will buy one(1chipNES) if the price is reasonable.
I can buy a clone one(NES/FC) about USD15 here for my kids to play.
The video quality is not good on LCD TV, but works fine on CRT TV.
Sometimes I play it(NES/FC) on my computer via emulator, sometimes I play it on the LCD TV via Wii NES emulator. I am very happy with the quality from emulators no matter PC or Wii version.
I have been dreaming to have a box which I can put synthesizable RTLs to emulate any arcade or console to play with it.
1chipMSX is a starting point. I would like to see if there is a standard platform for all maybe 8 bits consoles to be put in to play and to study.

BR,
Jinwar


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PostPosted: Sun Nov 14, 2010 10:06 am 
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jinwar wrote:
Hi All,

I really like to see the same thing happened as 1chipMSX on NES/FC.
http://en.wikipedia.org/wiki/1chipMSX
I will buy one(1chipNES) if the price is reasonable.
I can buy a clone one(NES/FC) about USD15 here for my kids to play.
The video quality is not good on LCD TV, but works fine on CRT TV.
Sometimes I play it(NES/FC) on my computer via emulator, sometimes I play it on the LCD TV via Wii NES emulator. I am very happy with the quality from emulators no matter PC or Wii version.
I have been dreaming to have a box which I can put synthesizable RTLs to emulate any arcade or console to play with it.
1chipMSX is a starting point. I would like to see if there is a standard platform for all maybe 8 bits consoles to be put in to play and to study.

BR,
Jinwar


You can buy a NOAC, but you can't play a lot of games. And no offence, if they do sell these, one buy won't mean much probably, especially not to get these awesome projects done faster. :3 If you like emulator, stick with it and just get a NES controller->USB device from RetroUSB. They're pretty nice.


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PostPosted: Sun Nov 14, 2010 5:20 pm 
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Quote:
You can buy a NOAC


Do you mean NOAC as http://encyclopedia.thefreedictionary.com/NES+on+A+Chip

If so, actually, the clone NES/FC I bought is a NOAC.
The forum seems not allow to attach photo, otherwise I can post a pretty small PCB of that for you.
The NOAC I have actually can play a lot of NES/FC games but bad video quality on LCD TV.


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PostPosted: Sun Nov 14, 2010 8:38 pm 
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Yeah but they don't have a lot of add ons and don't run all games right. They okay, but still not the real thing. :)


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PostPosted: Mon Nov 15, 2010 1:49 am 
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kevtris wrote:
Right now I am using a cyclone 3 25K model, same size chip (240 pins) as the previous model, but 2x more gate-age.

Cool! Do you find yourself using any Cyclone-III-specific technology for your NES that wasn't available in the old Cyclone-I that might prevent back-porting? I'm running into that problem with my NES with the Xilinx devices. I was originally supporting both Virtex-2 and Virtex5 but now I'm only supporting V5 because it just became too time consuming and too much of a pain to keep both versions up and running.

kevtris wrote:
I selected altera, because xilinx's programming environment is a huge steaming pile of poo. Buggier than a swamp in june, in #nesdev I watched people struggle with it; compiles that work but then the device doesn't, unless they downgrade the compiler.

I know exactly what you mean!! Stupid Xilinx!!! GRRRRR!!!!!!! And it hasn't changed one bit! Bah!! Haha, maybe I need to switch over to Altera for this....ugggh, yet another tool and technology to learn. :-/


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PostPosted: Mon Nov 15, 2010 2:18 am 
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jwdonal wrote:
Cool! Do you find yourself using any Cyclone-III-specific technology for your NES that wasn't available in the old Cyclone-I that might prevent back-porting?

I wouldn't imagine there'd be much in the NES that wouldn't be back-portable. The Cyclone III isn't very different - better PLLs and more RAM and I can't think of much else (probably I/O features & power considerations).

jwdonal wrote:
I know exactly what you mean!! Stupid Xilinx!!! GRRRRR!!!!!!! And it hasn't changed one bit! Bah!! Haha, maybe I need to switch over to Altera for this....ugggh, yet another tool and technology to learn. :-/

Another unsatisfied Xilinx user eh? I can't believe that they're still a major player with tools that suck big fat hairy dogs' balls. I've used them on occasion and I hate them with a passion. I've never met anyone who uses both that prefers Xilinx tools. And I've heard of plenty that go Altera and never look back. I urge you to make the switch - you'll never regret it!


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PostPosted: Mon Nov 15, 2010 10:00 am 
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jwdonal wrote:
kevtris wrote:
Right now I am using a cyclone 3 25K model, same size chip (240 pins) as the previous model, but 2x more gate-age.

Cool! Do you find yourself using any Cyclone-III-specific technology for your NES that wasn't available in the old Cyclone-I that might prevent back-porting? I'm running into that problem with my NES with the Xilinx devices. I was originally supporting both Virtex-2 and Virtex5 but now I'm only supporting V5 because it just became too time consuming and too much of a pain to keep both versions up and running.

kevtris wrote:
I selected altera, because xilinx's programming environment is a huge steaming pile of poo. Buggier than a swamp in june, in #nesdev I watched people struggle with it; compiles that work but then the device doesn't, unless they downgrade the compiler.

I know exactly what you mean!! Stupid Xilinx!!! GRRRRR!!!!!!! And it hasn't changed one bit! Bah!! Haha, maybe I need to switch over to Altera for this....ugggh, yet another tool and technology to learn. :-/


It directly ported over from the C1 to the C3, and could be easily backported if need be.

I put all the special vendor/chip specific stuff in a single verilog file though, so if I have to change devices/vendors/etc it should very easy to do so. Backporting to the C1 is kinda useless now since I think altera EOL'd it. I was on their page and they only show cyclone 2, 3, and 4 now.

Actually getting the NES to run on the new hardware was dead simple- it took maybe a day to fix it all up. I did use my verilog SDRAM module however, because I had to modify it for 16 bit wide RAM (to make it 8 bits wide for the NES using the byte enables and stuff). Buut, games ran first go after some minor hardware initialization stuff. Then it took about 2 months to convert it over from schematic to verilog, which let me fix a bunch of hacky stuff and bugs, and introduce some new bugs I'm sure.

Altera's dev environment is pretty easy to use though, and seems fairly bug free with regards to actually generating fusemaps and whatnot. It's really nice and I really like the code editor on it vs. other IDEs' code editors. I tried the ISE webpack (xilinx IDE) when I was considering using a xilinx part, but I ended up uninstalling it out of frustration and went with another altera part instead. Their chips might be nice but the dev software sure isn't.

(Also, I detest how xilinx uses marketing terms to describe their chip capacity. The whole "gate count" garbage isn't a very useful metric, since there's no definition of what a "Gate" really is. What I was reading awhile back is the gate count includes all the gates in the configuration and programming logic along with the "user gates". What really counts is how many complex logic blocks the chip has, which is directly related to what you get to put you design in.)

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PostPosted: Mon Nov 15, 2010 10:23 am 
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For people more familiar with CPLDs, where a macrocell roughly corresponds to one flip-flop, how many macrocells is a "complex logic block" worth?


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PostPosted: Mon Nov 15, 2010 2:22 pm 
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The altera chips use Logic Elements (LEs), which are a single bit register and a 4-input LUT with a wide variety of routing options. They're packed into Logic Array Blocks (LABs) in groups of 16, which are laid out in a grid pattern on the chip.


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PostPosted: Mon Nov 15, 2010 3:37 pm 
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ReaperSMS wrote:
The altera chips use Logic Elements (LEs), which are a single bit register and a 4-input LUT with a wide variety of routing options. They're packed into Logic Array Blocks (LABs) in groups of 16, which are laid out in a grid pattern on the chip.


The altera Cyclone chips use Logic Elements (LEs)... FTFY

More than a few people have written articles on comparing Altera and Xilinx logic resources. In some respects, you're comparing apples & oranges. Sometimes I swear they chose different architectures not for any technical reason, but just so they they couldn't be compared! :wink:


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PostPosted: Mon Nov 15, 2010 4:24 pm 
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tcdev wrote:
I swear they chose different architectures not for any technical reason, but just so they they couldn't be compared! :wink:

I wouldn't be surprised if that was 100% correct. Seriously.


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PostPosted: Mon Nov 15, 2010 10:17 pm 
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Who is the first one to start creating NES on FPGA?
kevtris or below?
http://crystal.freespace.jp/pgate1/nes/index.html
or
http://www.geocities.jp/team_zero_three ... on_minimig
or
http://cegt201.bradley.edu/projgrad/proj2006/fpganes/
or
...

Again, I will buy one if someone can sell a platform such as 1chipmsx or Minimig for reasonable price.


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