nesdev.com

facepalm.. sorry man, I just accidentally mangled your post. thought I was editing mine. I need to go to bed.

edit: OK, I hit the back button to recover it and hopefully have restored it

I must have made a typo in my previous test; with my kinda ugly memory dumper, I only ever see the same 512-byte pattern regardless of what all the higher address lines do.

Two different SST39SF040s have the same bytes at offsets $3B-$3D, so maybe that's a lot code (since it differs from Memblers's)

I wonder if those varying bytes are a date? 0E0C04 could be 2014-December-4 and 0F0601 could be 2015-June-1 ... The datecode on my two (with 0E0C04) is 1446, 46th week of 2014, or mid-November...

I just had a chance to check the date, and it is 1522 on that chip. June 1st was the first day of 23rd week, that's about the right time. That's kinda cool to be able to read that in the software.

This was certainly a very interesting read even though I just noticed it was a bit (very) old

Btw, are these assumptions correct?

-Everything is physically in 32kB banks.
-The tool just takes the same 16kB block and writes it one time in each 32kB bank, at your option, to mimmic a fixed-swappable configuration.

-this means that outside of the tool as-is, one can configure custom partitions; for example:
-8kB interleaved/fixed, 24kB swappable per bank, or vice versa.
-Have a 32kB bank and then a number of banks that behave like 16-16 ones.
-basically any partition you can think of to be useful for your project.

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http://www.frankengraphics.com - personal NES blog

You are correct.

32K banking allows for a surprising amount of versatility, including emulating fixed/switchable banks that aren't a power of two.

I can note something I would have preferred to have: That the register is mapped at $1000-$1FFF and $3000-$3FFF in addition to $5000-$5FFF and $7000-$7FFF (although the $3xxx mapping will rarely if ever be used, it is still there simply due to how the logic is working), and it is written regardless of whether you read from or write to those addresses (if you read, it writes the value read).

Other than that it look like good, I think.

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RAM and PPU registers are mirrored there.
https://wiki.nesdev.com/w/index.php/CPU_memory_map

I know that. (Those addresses would access both the RAM/PPU and the cartridge simultaneously, which can be useful, but regardless of that, it means one less bit of logic (two, if you also ignore R/W).)

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Would it be theoretically possible to remap the registers individually in a future revision, or is it too inconvenient hardware-side?

My impression so far has been that while it looks practical to have it all in one and the same register, it is actually a bit inconvenient code-wise since you need to load merge states with changes before writing.

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http://www.frankengraphics.com - personal NES blog

Separating things out into different registers will likely at least double the mapper logic required, so I'm guessing it wouldn't align with the Membler's goal with the mapper. The amount of discrete logic chips will start to compare to a small CPLD which could provide a much richer feature set. In reality once you start separating things into separate registers you're getting into the MMC1 scale mapper level.

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If you're gonna play the Game Boy, you gotta learn to play it right. -Kenny Rogers

Seems like a good size for a Greenpak.

Are prices of those guys posted anywhere? Looks like the slg46824 would be the best part to target as it's I2C in system programmable and also comes in more friendly TSSOP-20 packaging with high i/o and flipflop count in comparison to other versions (17 i/o & FF's). Other parts appear to have pretty good pricing available for purchase on their site $0.30-0.50ea if you can handle the 100-3k min qty. No indications of the slg46824's pricing though, shot off a sales inquiry to see what they have to say..

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If you're gonna play the Game Boy, you gotta learn to play it right. -Kenny Rogers

They stopped offering volumes less than 100 a couple years ago. Looks like the SL46824 is brand new too.

I'm a little confused by their claim that the '824 there supports 17 I/O—unlike some of the older ones, I don't see a way to turn off the I²C logic unit, so that's two pins permanently lost.

But I bet 15 I/O is still enough—for something that's the same features as GTROM but with three registers would require ... in: /rs a14 a13 a12 m2 d0 d1 d2 d3 ppua13 ; out: a15 a16 a17 a18 chra14 — that's exactly 15.

... oops, that doesn't include one input and output to invert R/W into W/R for self-flashing. Hm.