You'll want to make a mod 50 counter. I don't know VHDL so I'll explain in English:
Code:
counter is integer (6 bits)
at rise of clock_in:
if bit 5 of counter is 1:
subtract 21 from counter // that's 50 minus 29
else:
add 29 to counter
set clock_out to clock_in AND bit 5 of counter
You can make it slightly more steady with a double-pumped adder. Clock the divider on both positive and negative edges of the input clock (making an effectively 100 MHz counter) and then use a toggle flip-flop to feed the output
Code:
counter is integer (6 bits)
clock_out is integer (1 bit)
at rise or fall of clock_in:
if bit 5 of counter is 1:
subtract 21 from counter
set clock_out to clock_out XOR 1
else:
add 29 to counter
To get a more even clock than that, you'll need to add some analog means of filtering, such as a band-pass filter feeding an inverter or something.
Code:
_/‾\_/‾\_/‾\_/‾\_/‾\_/‾\_/‾\_/‾\_/‾\_/‾\... Input clock
_/‾\_/‾\_____/‾\_____/‾\_/‾\_____/‾\____... Single-pumped divider output
_/‾\___/‾‾‾\_/‾‾‾\___/‾\___/‾‾‾\_/‾‾‾\__... Double-pumped divider output
_,'‾`._,'‾`.__,'‾`.__,'‾`._,'‾`.__,'‾`._... Double-pumped followed by analog filter
‾‾\__/‾‾\__/‾‾‾\__/‾‾‾\__/‾‾\__/‾‾‾\__/‾... Double-pumped and filtered through inverter