It is currently Sun Oct 22, 2017 7:43 pm

All times are UTC - 7 hours





Post new topic Reply to topic  [ 14 posts ] 
Author Message
 Post subject: Help with clock divider
PostPosted: Wed Feb 03, 2016 9:05 am 
Offline
User avatar

Joined: Tue Dec 04, 2012 3:28 pm
Posts: 337
Location: Canada
I know this is an odd request for Nesdev, but can someone help me with VHDL for a clock divider? I'm using a 50MHz clock and trying to get it down to 29Mhz. I can't seem to get it to work.

This is how I have it now (based off of a template I found online):

Code:
entity clock is
   port ( CLKin: in std_logic;
          reset: in std_logic;
          CLKout: out std_logic);
end clock;
architecture arch of clock is

  signal counter: integer:=0;
  signal temp : std_logic := '1';
begin
process(CLKin,counter,reset)
begin
   if(reset='0') then counter<=0; temp<='1';
    elsif(CLKin'event and CLKin='1') then counter <=counter+1;
     if (counter = 29000000) then temp <= NOT temp; counter<=0;
     end if;
    end if;
   CLKout <= temp;
end process;
end arch;



Any idea as to what is wrong here?


Top
 Profile  
 
PostPosted: Wed Feb 03, 2016 9:27 am 
Online

Joined: Sun Sep 19, 2004 11:12 pm
Posts: 19115
Location: NE Indiana, USA (NTSC)
How clean does the 29 MHz clock signal have to be? By "clean" I mean close to steady timing and 50% duty. I ask because a simple divider will likely produce an aliased signal.


Top
 Profile  
 
PostPosted: Wed Feb 03, 2016 9:42 am 
Offline
User avatar

Joined: Tue Dec 04, 2012 3:28 pm
Posts: 337
Location: Canada
Its for a counter, so I'd say as steady as any counter IC. Not sure if they have any deviation or not with their clocks...


Top
 Profile  
 
PostPosted: Wed Feb 03, 2016 10:24 am 
Offline

Joined: Thu Aug 12, 2010 3:43 am
Posts: 1589
The problem is that 50 is not divisible by 29 so to stay steady you'd have to make some cycles last longer than others.


Top
 Profile  
 
PostPosted: Wed Feb 03, 2016 10:43 am 
Online

Joined: Sun Sep 19, 2004 11:12 pm
Posts: 19115
Location: NE Indiana, USA (NTSC)
You'll want to make a mod 50 counter. I don't know VHDL so I'll explain in English:
Code:
counter is integer (6 bits)
at rise of clock_in:
    if bit 5 of counter is 1:
        subtract 21 from counter  // that's 50 minus 29
    else:
        add 29 to counter
set clock_out to clock_in AND bit 5 of counter

You can make it slightly more steady with a double-pumped adder. Clock the divider on both positive and negative edges of the input clock (making an effectively 100 MHz counter) and then use a toggle flip-flop to feed the output
Code:
counter is integer (6 bits)
clock_out is integer (1 bit)
at rise or fall of clock_in:
    if bit 5 of counter is 1:
        subtract 21 from counter
        set clock_out to clock_out XOR 1
    else:
        add 29 to counter

To get a more even clock than that, you'll need to add some analog means of filtering, such as a band-pass filter feeding an inverter or something.

Code:
_/‾\_/‾\_/‾\_/‾\_/‾\_/‾\_/‾\_/‾\_/‾\_/‾\...  Input clock
_/‾\_/‾\_____/‾\_____/‾\_/‾\_____/‾\____...  Single-pumped divider output
_/‾\___/‾‾‾\_/‾‾‾\___/‾\___/‾‾‾\_/‾‾‾\__...  Double-pumped divider output
_,'‾`._,'‾`.__,'‾`.__,'‾`._,'‾`.__,'‾`._... Double-pumped followed by analog filter
‾‾\__/‾‾\__/‾‾‾\__/‾‾‾\__/‾‾\__/‾‾‾\__/‾... Double-pumped and filtered through inverter


Top
 Profile  
 
PostPosted: Wed Feb 03, 2016 10:50 am 
Offline
User avatar

Joined: Wed Feb 13, 2008 9:10 am
Posts: 578
Location: Estonia, Rapla city (50 and 60Hz compatible :P)
You need to count to a loooooot smaller number. 50000000 / 29000000 = 1.724...
You'll probably want to try to make a phase accumulator and use the highest bit as the clock output.
You also aren't gonna get a 50% duty cycle on the output clock, Tepples idea of using both clock edges will improve it a bit.

_________________
http://www.tmeeco.eu


Top
 Profile  
 
PostPosted: Wed Feb 03, 2016 2:48 pm 
Offline

Joined: Thu Aug 12, 2010 3:43 am
Posts: 1589
I have to admit it, exploiting analog filtering and then reinterpreting back as digital looks way clever. Would it improve if the filter-inverter part was done twice in a row?


Top
 Profile  
 
PostPosted: Wed Feb 03, 2016 3:32 pm 
Offline

Joined: Sun Apr 13, 2008 11:12 am
Posts: 6297
Location: Seattle
An extra round of filtering followed by quantization shouldn't really be any better than just a second order lowpass filter in the first place.

The analog way I've seen to do this is a tuned high-Q LC tank at the desired frequency.


Top
 Profile  
 
PostPosted: Fri Feb 05, 2016 12:40 pm 
Offline
User avatar

Joined: Tue Dec 04, 2012 3:28 pm
Posts: 337
Location: Canada
Ok, so to give an update here:

I changed my design to use a 30Mhz clock, so that it's much simpler and no division is needed. However... I still can't get this thing working.

Is there some sort of special function that needs to be done when adding a clock in a CPLD design? Like, do I need to specify something BECAUSE its a clock? I can't seem to find anything on it. I am implementing it in the Xilinx schematic editor, using a 8-bit bidirectional binary up/down counter (CB8X1).

The thing is, I know that my circuit works. If I implement a 74HCT193 (running at its own 29Mhz, but close enough to what I want) chip onto the board, wired to the same outputs the CPLD would use, the counting works fine and my LEDs respond as expected. But with the CPLD design NOTHING happens. It's like the clock isn't doing anything, and everything just sits there.

For reference I am using this oscillator - https://www.digikey.ca/product-detail/en/7X-30.000MBB-T/887-1221-1-ND/2119124

It's wired as follows: Pin 1 is unconnected, Pin 2 is GND, Pin 3 is output to my CPLD clock input, and pin 4 is 3.3V.


Top
 Profile  
 
PostPosted: Fri Feb 05, 2016 2:55 pm 
Offline
User avatar

Joined: Mon Apr 04, 2011 11:49 am
Posts: 1905
Location: WhereverIparkIt, USA
Check your clock input from the oscillator to the CPLD first with an oscope or similar to ensure your actually feeding the CPLD with a clock signal. Assuming you are then make sure you don't have any silly errors with pin assignments with your CPLD configuration, that's the most likely and first thing to check with a CPLD when things aren't behaving as necessary. If that doesn't turn up anything you'll have to double check your logic and I'd recommend using the test bench to apply a clock stimulus and look for your expected singals throughout the design including mid points etc.

There isn't anything specific needed to designate a signal as a clock source generally. Most CPLDs have specific pins denoted as clock inputs, but it isn't necessary to route your clock through that pin. It only becomes beneficial to route through that pin if you have a large amount of synchronous logic being driven by that clock. Your counter doesn't sound like it would fall under that category.

_________________
If you're gonna play the Game Boy, you gotta learn to play it right. -Kenny Rogers


Top
 Profile  
 
PostPosted: Fri Feb 05, 2016 4:20 pm 
Offline
User avatar

Joined: Tue Dec 04, 2012 3:28 pm
Posts: 337
Location: Canada
infiniteneslives wrote:
Check your clock input from the oscillator to the CPLD first with an oscope


Unfortunately I don't have access to a scope. Is there some way to test with a multimeter?


Top
 Profile  
 
PostPosted: Fri Feb 05, 2016 4:55 pm 
Offline

Joined: Sun Apr 13, 2008 11:12 am
Posts: 6297
Location: Seattle
It won't be very accurate, but you could try building a lowpass filter of known corner frequency and seeing what attenuated voltage comes out...

If you choose 1/RC=1MHz, then 30MHz should have be at 1/30th the nominal voltage. So a 5Vpp 30MHz clock when attenuated would become 167mVpp.


Top
 Profile  
 
PostPosted: Fri Feb 05, 2016 6:40 pm 
Offline
User avatar

Joined: Mon Apr 04, 2011 11:49 am
Posts: 1905
Location: WhereverIparkIt, USA
Alternatively you could skip that first step and move on to the other troubleshooting methods. But be prepared for heartache if those checks turn up nothing and you're still can't answer the important question of wether you have good input to your logic..

One other idea would be to feed your circuit with a slower speed clock you can be certain of. Something slow enough to see an LED flicker perhaps, test out your logic at slow speed you can measure without an oscope first. Then try the oscillator afterwards.

_________________
If you're gonna play the Game Boy, you gotta learn to play it right. -Kenny Rogers


Top
 Profile  
 
PostPosted: Tue Feb 09, 2016 1:23 pm 
Offline
User avatar

Joined: Tue Dec 04, 2012 3:28 pm
Posts: 337
Location: Canada
Welp, I still haven't made any headway at all. I've done the voltage tests lidnariq suggested (to the best of my knowledge) and everything SEEMS to be working...But it's not. I even pulled a clock that I KNOW was working on another board, and no luck there. So either my counter is crap or I'm doing things wrong.

So, seeing as I wasn't making any progress, I decided to buy an Altera Cyclone 2 DE1 board(I know, I could've gone with the Cyclone V, but i figured that was overkill for what I needed...and too expensive). Hopefully this will help me along, and ideally come in handy with future projects. It's got a built in 50Mhz, 27Mhz and 24Mhz clock, so I'm sure out of three of them I can figure out how to get one working :)


Has anyone here used that dev board before?


Top
 Profile  
 
Display posts from previous:  Sort by  
Post new topic Reply to topic  [ 14 posts ] 

All times are UTC - 7 hours


Who is online

Users browsing this forum: No registered users and 6 guests


You cannot post new topics in this forum
You cannot reply to topics in this forum
You cannot edit your posts in this forum
You cannot delete your posts in this forum
You cannot post attachments in this forum

Search for:
Jump to:  
Powered by phpBB® Forum Software © phpBB Group