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PostPosted: Fri Mar 03, 2017 5:33 pm 
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The 6845 is ... not obviously useful to me? Its big advantage is that it lets you switch between multiple pixel clocks, or multiple monitor scanrates, and cleanly let you pack RAM when your active screen isn't a power of two wide.

The contemporary version of it supported a maximum tile rate of 2.5MHz, and a maximum scanline length of 256 tiles. Obviously it could be sped up (as the VGA does..) 341 has two prime factors, so you could use 11-pixel-wide tiles, and fit 23 on-screen on a scanline of 31 tiles. But 11 is a pain...

For a fixed-rate system, it really feels like it just complicates things without obviously helping. Building a simple system to draw out a tilemap display is quite easy (e.g. the Sprint 2 arcade hardware or the PlayChoice 10 help screen are both quite simple)


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PostPosted: Fri Mar 03, 2017 6:00 pm 
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Location: NE Indiana, USA (NTSC)
Motorola 6845 datasheet

psycopathicteen wrote:
That's pretty dang interesting. Yeah I think that's a good idea. The only limitation is that lines would have to be an even number of pixels so you can't have 341 pixels/cycles per line.

The CRTC needs to be driven at character rate by dividing what the datasheet calls an "external dot counter". This means there already needs to be a divider in front of it, and the hsync signal from the CRTC could reload this divider to shorten or lengthen a character, allowing a wider choices of scanline period.

The NTSC standard specifies a total scanline period of 227.5 cycles of the color subcarrier. Assuming a 21.47 MHz master clock (six times color subcarrier), the standard scanline is 1365 master clocks. So for a TMS9918-style 5.37 MHz dot clock and 256 to 280 pixel* picture width, you could program the CRTC for a horizontal total of 42 characters (336 pixels; 1344 master clocks) and use some circuitry triggered by hsync to "stretch" one character by an additional 21 master clocks. Normally in a 240p system, you get 262 lines per frame, or 59605 cycles. But this would produce an annoying Neo Geo-style still pattern of chroma dots. That can be fixed by alternating the subcarrier phase from one frame to the next, which can be done by shortening the three vsync lines from 1365 to 1364 pixels, giving a dot crawl that's as perfect as it'll get.

The other way to do this is to divide the master clock by 3.5, giving 288 to 320 square pixels* out of a 390-pixel line. Program the CRTC for 48 characters (384 pixels) for the same 1344 master clocks, and use the same clock stretching.

* First pixel count is action safe area; second includes overscan area.


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PostPosted: Fri Mar 03, 2017 7:17 pm 
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Are 227.5 cycle scanlines really the best for pixel art? I think a comb filter would blur diagonal details too much.


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PostPosted: Sat Mar 04, 2017 11:28 am 
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You can probably do sprites on a microcontroller, but tile maps with discreet logic.


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PostPosted: Sat Mar 04, 2017 11:50 am 
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A lot of older arcade machines do sprites in discrete logic too. (e.g. look at the Sprint 2 or Pac-Man hardware: both provide a small number of non-multiplexed sprites).

The biggest difference between the NES and older hardware is the automatic multiplexing of sprites to ... uh, "blitters".

I've been kinda wanting to build an all-new-parts copy of the Pac-Man arcade hardware, but can't quite justify it.


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