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PostPosted: Fri Jun 02, 2017 12:15 am 
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nicklausw wrote:
NovaSquirrel wrote:
There's the eZ80 which has 24-bit registers, a 3-stage pipeline, and which ditches the z80's 4-bit ALU for a 24-bit one, so it's pretty much a suped-up fast z80 in every way. Would be cool to see that in something that's not an embedded system with fixed code; the closest I've seen are some of TI's newer calculators.

Man, they stole my idea almost a decade before I came up with it! [/sarcasm]

24bit registers buts it still 8bit ....

The 65CE02/new 4510 cpu fixes some of these issue in the 6502, it lets you do 24 and 32bit indirect indexed It would be interesting to see what a 50Mhz eZ80 vs a 50Mhz 4510 could do...

Also there is a 6502.orgs 65Org16, although not sure it is still "8bit"


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PostPosted: Fri Jun 02, 2017 12:20 am 
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Other ideas I've been musing with is What could you achieve with reworked motherboards, take components of the day but rework them. Say you have a PPU and then add another chip that does sprites, a TMS something ;) then put another 6502 are higher clock, so you have a GPU cpu and an game CPU, more of an arcade machine design. The C128 offers a lot of potential in this area.


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PostPosted: Fri Jun 02, 2017 2:13 am 
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the eZ80 @ 50mhz is apparently stated to be equivalent to a z80 clocked to 150mhz when used with fast enough memory. eZ80 comes in various variations (ROMless, flash, sram, 20/50mhz). The price is normally 8-7, occasionally up to 12 EUR (for 50mhz variants) and down to 4,5 EUR (for 20mhz) when ordered by the hundreds.

The 4510 has those two fancy CIA:s. Mouser and digi-key doesn't seem to have them in stock.

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PostPosted: Fri Jun 02, 2017 2:33 am 
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dougeff wrote:
There doesn't seem to be a homebrew scene for TG16/PCE. It's a shame. I know almost nothing about the system. Never saw one in my life.

That's a shame. PC Engine is literally my favourite console system of all time. There's so much great stuff on it, especially its arcade ports. It's like a proto-Saturn, but I like it a lot more.

It's sad that a lot of people still perceive the system as "obscure". In Japan it was bigger than Sega.


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PostPosted: Fri Jun 02, 2017 3:49 am 
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FrankenGraphics wrote:
the eZ80 @ 50mhz is apparently stated to be equivalent to a z80 clocked to 150mhz when used with fast enough memory. eZ80 comes in various variations (ROMless, flash, sram, 20/50mhz). The price is normally 8-7, occasionally up to 12 EUR (for 50mhz variants) and down to 4,5 EUR (for 20mhz) when ordered by the hundreds.

The 4510 has those two fancy CIA:s. Mouser and digi-key doesn't seem to have them in stock.

Yeah but I'm talking about this version which is a open source FPGA core http://c65gs.blogspot.com.au/2016/04/ov ... today.html he had to pull back on the 192Mhz version as people complained it wasn't 8bit feel still. 1Mhz 6502 is basically near to 3Mhz Z80, so a 48Mhz 4502/10 and a 150Mhz Z80 would be "Game On" ;)


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PostPosted: Fri Jun 02, 2017 9:56 am 
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Sumez wrote:
It's sad that a lot of people still perceive the system as "obscure".

I think it's about at the level of obscurity as the Neo Geo. "Obscure" is the CPS changer: http://www.nintendolife.com/news/2015/0 ... me_console


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PostPosted: Fri Jun 02, 2017 10:26 am 
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I've never seen the CPS Changer,thanks for the link Espozo.


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PostPosted: Fri Jun 02, 2017 10:29 am 
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Sumez wrote:
dougeff wrote:
There doesn't seem to be a homebrew scene for TG16/PCE. It's a shame. I know almost nothing about the system. Never saw one in my life.

That's a shame. PC Engine is literally my favourite console system of all time


I owned one and so did friends in high school,great system.


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PostPosted: Fri Jun 02, 2017 6:35 pm 
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As I understand it, one of the main bottlenecks of the day was memory. How fast were RAM/ROM chips from circa 1985, and what does that translate to in terms of clock speeds?

For example, the NES PPU reads one byte every two pixels. Was that purely to save on pins, or does it have to hold the address lines steady for the entire two clocks for the memory to keep up?

If the latter, the only way to get more than 2bpp on a 256x240 BG layer would be to do like the SMS, and use a 16-bit data bus, in which case 3bpp (which I'm something of a fan of) doesn't make a whole lot of sense... unless you use 16-pixel-wide tiles, I guess. Or interleave the first two planes and simply ignore half of every third-plane read, using 3bpp solely to cut down on pattern memory.

I'm rambling again, sorry. :P


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PostPosted: Fri Jun 02, 2017 7:16 pm 
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Rahsennor wrote:
As I understand it, one of the main bottlenecks of the day was memory. How fast were RAM/ROM chips from circa 1985, and what does that translate to in terms of clock speeds?

For example, the NES PPU reads one byte every two pixels. Was that purely to save on pins, or does it have to hold the address lines steady for the entire two clocks for the memory to keep up?

If the latter, the only way to get more than 2bpp on a 256x240 BG layer would be to do like the SMS, and use a 16-bit data bus, in which case 3bpp (which I'm something of a fan of) doesn't make a whole lot of sense... unless you use 16-pixel-wide tiles, I guess. Or interleave the first two planes and simply ignore half of every third-plane read, using 3bpp solely to cut down on pattern memory.

I'm rambling again, sorry. :P


Maybe it could have a 2bpp background, but a choice between 2bpp 3bpp or 4bpp sprites.


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PostPosted: Fri Jun 02, 2017 9:13 pm 
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It might be worth just recap'ing what the OneBus VT03's capabilities were, for comparison:
* Integral MMC3 with outer banks (comparable to the COOLBOY cart)
* choice of 16px wide 2bpp sprites or 8px wide 4bpp sprites (or 8px wide 2bpp sprites) - but regardless limited to 8 per scanline
* option for 4bpp backgrounds
* option to switch from NES-normal 4+0+2 bit HSL to 4+4+4 bit HSL color specification
* full X,Y lightpen support in hardware
* One extra whole APU - but no second functioning DPCM DMA unit
* Integral asynchrous serial port


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PostPosted: Fri Jun 02, 2017 9:52 pm 
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Another alternative for video rather than the common way or the video instruction set is something involving the 6845 CRTC (which is what was used on PC), which allows the tile height to be controlled by software, as well as how many tiles per scanline, and other stuff (including lightpen support). (The 6845 CRTC works horizontally entirely in tiles and not in pixels. You must add external hardware to implement pixels.)

Still, I think having a video instruction set might help better (it is a kind of display list, like ANTIC has, although my idea is more capable, although still simple). You will still have to decide what video registers you want though; you could use a superset of the 6845 registers I suppose.

The background could be made as whatever bpp you want depending how many clock cycles are available; you could have 4bpp perhaps, and video registers will specify the base address of the tiles for each plane (which have to be a multiple of 256), and then the display program can alter these per scanline to display taller tiles. This would enable background tiles to be flipped vertically, although not horizontally.

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PostPosted: Sat Jun 03, 2017 2:04 am 
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Myask wrote:
Bregalad wrote:
Come on, this topic has already been discussed over and over here and here.

Where and where?

Sorry, I messed up when editing the PHP links. I edited them (including in the quote just above) so now they're fixed and points to the two topics where extremely similar matters were being debated (and those are both recent topics).


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PostPosted: Sat Jun 03, 2017 10:10 am 
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I decided to make a PPU register map for this fictional PPU

Code:
$xx00
bits 0-7 write:   IRQ fire position
bits 0-7 read:   scanline position

$xx01:
write
bit 0:      grayscale
bit 1:      color de-emphasis cyan
bit 2:      color de-emphasis magenta
bit 3:      color de-emphasis yellow
bit 4:      BG enable
bit 5:      sprites enable
bit 6:      IRQ enable
bit 7:      NMI enable

read
bit 0:      scanline position MSB
bit 6:      in H-blank
bit 7:      in V-blank

note: reading this register clears IRQ and NMI signals, but not IRQ and NMI enable

$xx02
bits 0-7:   x position

$xx03
bit 0:      x position MSB
bit 1:      ???
bit 2:      sprite height (not sure if needed)
bit 3:      left-most 8 pixels mask enable
bits 4-5:   BG patterns table select
bits 6-7:   sprite patterns table select

$xx04
bits 0-7:   y position

$xx05:
bits 0-1:   PPU memory
      00: VRAM increment by 1
      01: VRAM increment by 64
      10: Color RAM
      11: Sprite RAM
bits 2-3:   ??
bits 4-7:   name table select   

$xx06/07
bits 0-15:   PPU address bus port

$xx08:
bits 0-7:   PPU data bus port


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PostPosted: Sat Jun 03, 2017 3:31 pm 
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Should grayscale bit to disable the colour burst signal?

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