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PostPosted: Tue Jan 09, 2018 11:46 am 
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TOUKO wrote:
The 65xxx classic design is a 2 phase CPU, each phase access to the ram at 1/2 cycle, this is why 2x the CPU frequency ram is needed, if you redesign your CPU to be " a 1 phase" like the hu6280 you need RAM to be at the same frequency than the CPU,no cost added or something,all is the same, it's so hard to understand ???

A 1-phase design at twice the clock frequency would increase the throughput, but not quite double it. For one thing, it would need a lot more "internal operation" cycles for address generation, such as adding base addresses to indexes in LDA aaaa,X. There'd be no more hiding address generation in phase 1 for indexed loads that don't cross a page. The HuC6280 indeed uses an extra cycle for unindexed direct page and absolute addressing, and it has the page crossing penalty cycle for indexing even if no page is crossed. But with more pipelining, as seen in ARM and friends, I guess it could use that internal operation cycle to fetch the first byte of the next instruction.


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PostPosted: Tue Jan 09, 2018 12:06 pm 
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i agree, but what's better ,to have a 1 cycle penalty for some ram access and running @5.36mhz or to stay with the 2.68 ??
It was the simplest solution if you wanted to stay with the same RAM/ROM,because the 2 phase seems in fact useless if no external component needs to access to shared RAM with the CPU .
Mitsubishi has even designed a 65816 clone with a 16bit bus .


Last edited by TOUKO on Tue Jan 09, 2018 1:23 pm, edited 1 time in total.

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PostPosted: Tue Jan 09, 2018 12:43 pm 
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Quote:
it's not as common as the ADD instruction for instance (oh my bad, the 65C816 doesn't have ADD instruction :lol: )


Except in situations where the carry bit is expected to always be cleared.


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PostPosted: Tue Jan 09, 2018 12:54 pm 
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TOUKO wrote:
the 2 phase seems in fact useless if no external component needs to access to shared RAM with the CPU .

The 6502 and 65816 were used in unified memory architecture computers, such as the Apple II and Commodore 64. Their memory controllers include a multiplexer to let the video hardware access memory during phase 1 and the CPU access the same memory during phase 2. I agree that it's not ideal when CPU and VDC/VDP/PPU are in separate address spaces. But more engineering time spent on making the 65816 into a 1-phase CPU would have detracted from engineering time to get things like multiplane scrolling, color math, and affine background transformation working on the PPU.


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PostPosted: Tue Jan 09, 2018 1:10 pm 
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Quote:
But more engineering time spent on making the 65816 into a 1-phase CPU would have detracted from engineering time to get things like multiplane scrolling, color math, and affine background transformation working on the PPU.

yes, but ricoh who did the snes's CPU make the CPU nintendo wanted IMO, nothing more,and not the best they could.
It's also the strength of the 65xxx serie, to be easily customisable(that's why hudson was able to do the hu6280) , which did not seem to be allowed with the 68k until 92/93 i think (but not sure) .

what i wanted to say is nintendo did not wanted to spend more time/money with this because:
1- it was too late for that(i think the CPU was already in production(i think the snes was planned for 88/89 at start,plus it was cheap)
2- nintendo knew that it could be upgraded easily

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Except in situations where the carry bit is expected to always be cleared.

Yes .


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PostPosted: Wed Jan 10, 2018 2:19 am 
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psycopathicteen wrote:
Quote:
it's not as common as the ADD instruction for instance (oh my bad, the 65C816 doesn't have ADD instruction :lol: )


Except in situations where the carry bit is expected to always be cleared.


It was a joke replying to Touko about its BCD stuffs, still having a proper ADD instruction instead of ... BCD mode for instance (^^) would have be really handy ;)


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PostPosted: Wed Jan 10, 2018 5:04 pm 
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Decimal mode has all of two instructions devoted to it - SED and CLD. That's not very many addressing modes for a hypothetical ADD.

Even if you were to remove all instructions dealing with the status register except REP and SEP (this includes SEC and CLC), you still wouldn't be at parity with ADC, which has 15 opcodes devoted to it. You could use WDM as a prefix instruction, but that's kinda pointless as it takes just as long as CLC or SEC. It's only one byte, so maybe you could redesign the chip a bit to handle it in one cycle, but it's still slower than having an actual ADD, and it doesn't save any memory vs. the current setup.

This is one reason why a fully 16-bit 65xx could have been good. As many opcodes as you want, on top of doubled bus throughput, or (nearly) quadrupled if you were to go to 1-phase. Imagine that in the SNES... Apple would never have agreed to use it in the IIGS because it would have made the Macintosh look sick, even with the 2-phase design it would probably have needed for that application...

...

Just thought of something - maybe you could replace the decimal mode bit with an ignore carry bit. Then again, that seems cumbersome and error-friendly...


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PostPosted: Wed Jan 10, 2018 7:23 pm 
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93143 wrote:
You could use WDM as a prefix instruction, but that's kinda pointless as it takes just as long as CLC or SEC.

How about a perspective that ADD already is a 2-byte instruction, with CLC as the prefix? If you don't care about binary backwards compatibility you could just swap it so that ADD is the regular instruction, and ADC requires the prefix. Regular addition would get one byte smaller, and 16-bit/32-bit addition would remain the same size (CLC, ADC, ADC ---> ADD, prefix, ADD)


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PostPosted: Wed Jan 10, 2018 8:43 pm 
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That's actually how the Super FX works. The ADD Rn instruction is one byte, with four bits for the opcode and four for the operand register Rn, while ADC Rn is a macro instruction consisting of ALT1 followed by ADD Rn. Using ALT2 instead of ALT1 gets you ADD #n, an immediate add with a 4-bit operand, and ALT3 turns it into ADC #n.

The Super FX is another example of a 16-bit chip that would have benefited massively from 16-bit external busing...


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PostPosted: Thu Jan 11, 2018 2:53 am 
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Quote:
This is one reason why a fully 16-bit 65xx could have been good. As many opcodes as you want, on top of doubled bus throughput, or (nearly) quadrupled if you were to go to 1-phase. Imagine that in the SNES... Apple would never have agreed to use it in the IIGS because it would have made the Macintosh look sick, even with the 2-phase design it would probably have needed for that application...

i agree,but nintendo taken the cheapest way as usual, and lunched the SA-1(which is a monster) later :?

It seems the audio RAM to be psram at 120/100 ns, is it really needed to be so fast ??


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PostPosted: Thu Jan 11, 2018 8:05 am 
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TOUKO wrote:
It seems the audio RAM to be psram at 120/100 ns, is it really needed to be so fast ??

Audio RAM in the Super NES has to serve both the S-SMP (a 65C02 in drag) and the S-DSP, for a total of 3.07 MHz. I don't know those chips' memory access timing parameters. Has anyone here taken a scope to their address lines to see how fast they settle?


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PostPosted: Thu Jan 11, 2018 11:07 am 
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Quote:
I don't know those chips' memory access timing parameters

The audio RAM is PSRAM 120/100 ns for sure .

The chips reference is LH5P832N-12T

https://gamesx.com/wiki/lib/exe/detail. ... spc700.jpg

http://www.datasheetcatalog.com/datashe ... N-12.shtml

Quote:
Of course :) Free to you to think whatever you want, at least this time you said "for me" in your second sentence, this is already a progress ;)

Thanks to apply your advices also for you,because you speak always as a fact because you are convinced of it.
At least, I'm talking with evidence (which has already been done , and interviews), you, you often talk about what you think, even if we prove that you are wrong.


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