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PostPosted: Mon Apr 23, 2018 3:24 pm 
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Oziphantom wrote:
Because ARM was this tiny little British company from the people that made the Spectrum and nobody had heard of them.


Yeah, pretty much that. I don't know what the situation was in 1986 or whenever, but I'm sure it was a huge deal that 68000 was licensed to many manufacturers. I don't have a lot of 68K machines, but it seems like whenever I look at a board with one, I don't know if I've ever seen an actual Motorola, it's always a Hitachi or something else. If ARM was single-source at the time (I have no idea actually), there better be a huge advantage to designing it into something, because you could potentially be waiting a long time to get the parts you need for production.

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I also thing we are now in a post RISC world, I mean MIPS is dead, SPARC a memory, ARM now has NEON, and JAVA VM byte code instructions so its long past being "RISC". PPC dead. Scalar Super Computers distant memory ;)


Don't forget all the embedded computers we are surrounded with, it's out of sight, out of mind. Lots of stuff embedded in ASICs and stuff that we use all the time, they're just not "personal computers" of course. I've heard that MIPS pretty much dominates routers and such, 6502 at some point was big in automotive, a while back Chuck Peddle said he was designing a USB 3.0 controller that had something like 6 6502 cores running inside it, and in recent years I'd heard that Renesas is the company that was selling more CPUs than anybody else. I'm a big tech dork and I'd have to say Renesas is a company that I've heard of, but that's about the extent of my familiarity.


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PostPosted: Mon Apr 23, 2018 4:11 pm 
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Renesas is basically Hitachi, as far as I know. They're big on selling 68k emulation cores in embedded systems.

And yeah, Wikipedia link: https://en.wikipedia.org/wiki/Renesas_Electronics

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PostPosted: Tue Apr 24, 2018 9:56 am 
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Oziphantom wrote:
Because ARM was this tiny little British company from the people that made the Spectrum and nobody had heard of them.
It's irrelevant to the discussion but Sinclair made the Spectrum, not Acorn. Chris Curry did leave Sinclair to become one of the founders of Acorn, but were unquestionably different companies.

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PostPosted: Tue Apr 24, 2018 10:19 am 
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memblers wrote:
Don't forget all the embedded computers we are surrounded with, it's out of sight, out of mind.

And not just household things, but also in industrial automation and control, healthcare, the military.. Sometimes all you want is a small, stable, timing critical system where you know how every cycle is spent.

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PostPosted: Sun Apr 29, 2018 11:05 am 
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If I was designing a CPU in the late 80's for a game system, I would probably design a 16-bit RISC CPU with 8 registers, a 16-bit data and 16-bit addressing.


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PostPosted: Sun Apr 29, 2018 1:26 pm 
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Ehh.... even in hindsight, I don't think that's a good compromise. RISC architectures really benefit from having more registers (every time you have to spill to memory hurts them a lot more because they don't have complex addressing modes), and with only 8, x86-32 may be the most limited number of registers in something that's not accumulator-based (6502, 12/14/16-bit PIC, 8051)

(8080/Z80 is its own funny thing, with 4 to 15 registers depending on specific variant (prime registers, IX, IY) and how you count (split 8-bit/fused 16-bit).)

The 68k had 16, as does ARM, x86-64, 24-bit PIC, MSP430. SPARC, MIPS, SuperH, PPC, AVR have 32.

You might take a closer look at the MSP430 ISA.


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PostPosted: Sun Apr 29, 2018 2:08 pm 
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Even the Super FX had 16 registers. However, it was severely hobbled by its 8-bit instruction size, which may have been due to targeting one instruction per cycle (kinda) while using SNES cartridge memories (outside the instruction cache it was 3-5 depending on speed, and 6-10 would have been even worse). I wonder what it would have cost to go to 16-bit instructions with 16-bit or dual 8-bit memories and just use the bottom bit of SNES addresses as a half-word strobe or chip select (this would also have massively improved pixel buffer throughput). On the other hand, the instruction cache might have felt even smaller unless it were expanded... Also, reading from RAM was horribly expensive because there was no data cache and no way to preload - I think the PLOT circuitry probably took precedence here.

It also had echoes of accumulator-based design, in that it defaulted to using R0 if you didn't specify FROM, TO, or WITH. A number of instructions used 4-bit opcodes and 4-bit operands (to specify a register), and using R0 as both the other operand and the destination, or even just one or the other, could be much faster than using arbitrary registers for both.

...and I just realized that with 8 registers, you could specify both operands and the destination in a single 16-bit instruction and still have 7 bits of opcode left... on the other hand, I've programmed the Super FX before, and I was very glad I had as many registers as I did...


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PostPosted: Sun Apr 29, 2018 7:13 pm 
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I think having zero page addressing on a RISC cpu is a good idea.


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PostPosted: Sun Apr 29, 2018 7:56 pm 
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Or at least fast [Rn+dd] addressing, as 68000 and MIPS have. Under classic Mac OS on 68K, each running application got its own 32K of space in RAM for a struct called its "A5 world." This was used to store global variables and the like, as the actual low memory was reserved for the operating system.


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PostPosted: Mon Apr 30, 2018 12:10 am 
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To paraphrase Colin Chapman "All CPUs gain weight". So RISC moves towards CISC, CISC never moves towards RISC. The lines get bllury. Is an AVR really RISC or is it just because its 8 bit and therefor not really a x86 thus RISC. It almost seems RISC means "its not a x86/a64" ;)

To get around the RAM speeds and because the PS2 is built like an Amiga, it has Scratch Pad RAM for high-speed access. Sadly ( well actually kind of worked out better in the long run) the PSP didn't get Scratch Pad RAM... nor did the PS3, which would have really helped for those Float<>Int conversions...


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PostPosted: Mon Apr 30, 2018 12:44 am 
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Oziphantom wrote:
To paraphrase Colin Chapman "All CPUs gain weight". So RISC moves towards CISC, CISC never moves towards RISC. The lines get bllury. Is an AVR really RISC or is it just because its 8 bit and therefor not really a x86 thus RISC. It almost seems RISC means "its not a x86/a64" ;)
That the 12/14/16-bit PICs' documentation refers to it as a RISC ISA is endlessly amusing to me.


"Not a 68k, not an x86, not a PDP11, not a VAX. Wait, what are those last two?" Now I want to see a RISC machine that runs out of drum memory.


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PostPosted: Mon Apr 30, 2018 5:39 am 
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tepples wrote:
Or at least fast [Rn+dd] addressing, as 68000 and MIPS have. Under classic Mac OS on 68K, each running application got its own 32K of space in RAM for a struct called its "A5 world." This was used to store global variables and the like, as the actual low memory was reserved for the operating system.


Yeah, there would be a [5bit + Rn] addressing mode. Or 6bit, if there's enough space for it.


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PostPosted: Mon Apr 30, 2018 6:36 am 
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Oziphantom wrote:
Is an AVR really RISC or is it just because its 8 bit and therefor not really a x86 thus RISC. It almost seems RISC means "its not a x86/a64" ;)


The STM8 is advertised as an 8bit CISC processor despite high resemblance to 6502 with A,X,Y,SP,PC, & condition registers plus zero page. Compared to the 6502 it feels like the STM8 has an instruction for any operation you can think of plus a dozen you never think to use. It also has 18 different addressing modes, so seems STmicro is able to tell CISC from RISC.

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PostPosted: Tue May 01, 2018 4:45 am 
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I've always wondered but never asked, is the CISC/RISC denomination pretty much arbitrary? Problem is that it seems there's no real cutoff (or at least I'm not aware of it); people don't seem to know where the 65XX family falls.

I've got to say, seeing all these old, no longer used processor architectures is a bit depressing. :lol: People often like to say that the Saturn/PS1/N64 was the last console generation where the hardware was meaningfully different, and while the graphics are much more similar, I'd probably give this distinction to the Dreamcast/PS2/GameCube/Xbox; it's cool how every single system used a different processor architecture and kind of shows how different the landscape was then, I think. ARM went up through the ranks under it's own merit, but the one thing that's always bothered me is x86; we're still using the same architecture as a now 40 year old processor, although that might not be too fair of a comparison because of how much has been added. I don't know if it's lasted over the years because it's truly a great design, or rather Intel's massive market share and the desire to keep backwards compatibility.


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PostPosted: Tue May 01, 2018 5:09 am 
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I think "RISC" means no instructions take longer than 2 cycles, and operands have to fit inside the instruction word.


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