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PostPosted: Mon Feb 11, 2019 9:36 pm 
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Either at the end of a section (like the .text section), or where you put in .pool to manually force a literal pool at that location. Usually a compiler generating ASM functions will stick a literal pool at the end of every function.

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PostPosted: Mon Feb 11, 2019 11:14 pm 
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Just out of curiosity, what ARM assemblers for x86 machines are available? I only found FASMARM, but I figure there has to be more than that.


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PostPosted: Mon Feb 11, 2019 11:47 pm 
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GCC cross compilers for ARM (such as DevKitARM) include the GNU Assembler.

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PostPosted: Thu Feb 14, 2019 10:10 pm 
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I have to say that I've grown to appreciate RISC more in the past year or so. My computer achitecture class is teaching 32-bit MIPS and I got a crash course on ARM thumb-0 in one of my classes last year. I like ARM a bit more though in that its instructions seem more similar to 6502, which I guess you could say is my native assembly language. Is there a general consensus on which is superior (MIPS/ARM) in terms of its application for embedded systems?

It makes me interested in thinking about what something like 65xx or Z80 would look like if it had been extended to 32/64 bit, before the whole RISC/CISC debate was really a thing.


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PostPosted: Thu Feb 14, 2019 11:11 pm 
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Sogona wrote:
It makes me interested in thinking about what something like 65xx or Z80 would look like if it had been extended to 32/64 bit, before the whole RISC/CISC debate was really a thing.

Off-topic, but: you're probably unaware of the ill-fated 65832 (obviously CMOS): https://downloads.reactivemicro.com/Ele ... asheet.pdf

Every time I read that preliminary data sheet I get sad. Still limited to 3 registers (1 "main" register + 2 indexing-only), no native mul/div, blah blah. The additional addressing modes are not "super" helpful either. It really wasn't a CPU that the 90s would have benefit from, so it doesn't surprise me the 65816 was where it pretty much ended. 68K and x86 "won". And since then, we've been "stuck" with x86 and PC architecture, the latter of which at this point is *makes cat vomit noises*.


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PostPosted: Thu Feb 14, 2019 11:44 pm 
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Sogona wrote:
Is there a general consensus on which is superior (MIPS/ARM) in terms of its application for embedded systems?
I mean, honestly, most ISAs are equally ok for embedded systems. 8051s clocked at 100MHz were typical a decade ago..

Currently there seem to be more ARM licensees than any other ISA, but that's just a comment about mindshare, not suitability. Personally, I hope we see more RISC-V cores.

koitsu wrote:
with x86 and PC architecture, the latter of which at this point is *makes cat vomit noises*.
So you've played with Sun's and/or SGI's x86-based offerings?


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PostPosted: Fri Feb 15, 2019 1:38 am 
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lidnariq wrote:
with x86 and PC architecture, the latter of which at this point is *makes cat vomit noises*.
So you've played with Sun's and/or SGI's x86-based offerings?

To clarify: I'm not particularly fond of x86 (I stopped bothering to follow it with the introduction of the 486, and it seems I picked a good time to bow out, for my own sanity. A lot of present-day x86 code I can't even read due to all the extensions and ridiculousness, throw things like LOCK RMW instruction prefixes on top of the mix for SMP and I'm like "yeah, I'm done". Then you got the IDT, the GDT and LDT, MSRs, PAE, SMM/SMI, VT, *plus* all the nuances of x64... Yeah, no thanks. I sadly ever had the opportunity to play with PowerPC or Alpha at the time, though to be fair those are both RISC.

But I'm *really* not fond of PC architecture in general at this stage. I would classify it as quite possibly the longest-running hack-kludge tech project that humanity has ever kept going. There was a point in the mid-90s where a single person could just about understand the architecture -- now, we're so far from it that nobody can -- yet nearly all (and I do mean ALL!) the legacy support still in place for numerous reasons. Can you even remember all the bus types at this point (I can remember most of them, even wonky crap like MGA). We've learned a lot over the past ~40 years, but from all the corporate committees driving "standards" that are an abomination (APICs, ACPI, TPM, and UEFI all come to mind. I'd almost include USB but that's really not PC-specific) I don't think anyone in PC-land will ever stop and say "we should really just start over" because that'd a huge undertaking and would be killing the cash cow.

For example, if you've ever used a Sparc, there's a lot of things there that architecture-wise felt like no-brainers and just worked -- concepts like OpenBoot and having a native serial console from the get go.

For this reason, I think overall, ARM architecture (obviously also RISC) is at least a breath of fresh air. Admittedly I don't follow it to the level I should, but that may change for me given some things I can't really talk about (professional reasons).


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PostPosted: Fri Feb 15, 2019 2:37 am 
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What is superior is determined like you'd think, money. How much per cpu, per board, per coder, are there ready libraries so you need less coding...

ARM is popular, but it used to be that MIPS was cheaper for a certain cpu level. Then your use case may need a specific accelerator/DSP/whatever, which limits choices. I've recently done both MIPS and POWER things, PPC is nice too, even if it's not used much in embedded anymore.


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PostPosted: Fri Feb 15, 2019 4:42 pm 
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I looked up ARM Cortex-M0 instruction set and I was disappointed that indexed addressing only has a 5-bit offset, but then I realized that you get "6-bit" range when using 16-bit loads/stores, and "7-bit" range with 32-bit loads/stores, which is enough for object memory slot accessing.


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PostPosted: Fri Feb 15, 2019 9:51 pm 
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koitsu wrote:
But I'm *really* not fond of PC architecture in general at this stage. I would classify it as quite possibly the longest-running hack-kludge tech project that humanity has ever kept going. There was a point in the mid-90s where a single person could just about understand the architecture -- now, we're so far from it that nobody can -- yet nearly all (and I do mean ALL!) the legacy support still in place for numerous reasons.
This is not true, lots of instruction sets have been dropped over the years, they are up to the point of dropping some SSE instructions, so I would think that 8086-MMX would all be dropped as well. The "drivers" offer support for such instructions in that they emulate them on modern CPUs. There was an interesting talk by an AMD engineer at one of the security conferences going on about CPU errata and patching. Where he mentioned "we are finally dropping XXX set of instructions" sadly I've not been able to find in a search. I think it was also the same talk where Apple biged-up their Hunt For Red October levels of security for iCloud.

Also if you want to look at the very current PC landscape, ARM PCs are making another stab. In you can get a HP Envy X2 with either a snapdragon ARM processor or an Intel processor. The rumors keep circling for ARM macs.

However RISC is basically dead, although RISC-V is making a comeback, and The Raspberry Pi foundation just became a silver tier member, so RISC-V 'pi' might be in the works which would be nice. I think RISC-V has a shot, as people love free and the pure open source nature of it has the Linux diehards in a froth.

For a 32bit 6502, the Mega65's version of the 4510 has 24 and 32bit extension, however it is still a "6502", not sure if it also adds the Z register.

PPC is rubbish and it shocking how it is still being used..

MIPS was good but it is now very old and ARM has kept marching towards CISC and has SIMD cores, so bang for buck I imagine ARM will slaughter MIPS. I'm not sure that a PSP will really out do a DS in terms of CPU power, yes the PSP is more powerful but I don't think its 3.5x as powerful for its 3.5x clock rate.


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PostPosted: Fri Feb 15, 2019 9:58 pm 
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I looked at RISC-V and what's up with the weird scrambled immediate encoding?


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PostPosted: Fri Feb 15, 2019 10:34 pm 
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To get more speed, you need more instructions per fetch, so it has a pile of options to encode things smaller and add extra instructions on the tail.. its still RISC of cause ;) There is some info on how it works conceptually and compared to ARM and am64 here https://www.youtube.com/watch?v=Ii_pEXKKYUg


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PostPosted: Sat Feb 16, 2019 7:00 am 
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psycopathicteen wrote:
I looked at RISC-V and what's up with the weird scrambled immediate encoding?

Immediate operand values on RISC-V are scrambled to reduce multiplexers (muxes) inside the CPU, so that a particular operand (destination or first source) can always appear in the same bit position within the opcode. Each mux adds die area and gate delay. Die area increases power consumption and reduces area that can be used for data cache. Gate delay reduces maximum clock rate.

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PostPosted: Sat Feb 16, 2019 11:29 am 
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I found this page with an explanation. What's also interesting is that bit 31 is always the sign bit.

https://stackoverflow.com/questions/394 ... g-variants


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PostPosted: Sat Feb 16, 2019 9:10 pm 
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koitsu wrote:
Sogona wrote:
It makes me interested in thinking about what something like 65xx or Z80 would look like if it had been extended to 32/64 bit, before the whole RISC/CISC debate was really a thing.

Off-topic, but: you're probably unaware of the ill-fated 65832 (obviously CMOS): https://downloads.reactivemicro.com/Ele ... asheet.pdf

Every time I read that preliminary data sheet I get sad. Still limited to 3 registers (1 "main" register + 2 indexing-only), no native mul/div, blah blah. The additional addressing modes are not "super" helpful either. It really wasn't a CPU that the 90s would have benefit from, so it doesn't surprise me the 65816 was where it pretty much ended. 68K and x86 "won". And since then, we've been "stuck" with x86 and PC architecture, the latter of which at this point is *makes cat vomit noises*.


Wow, only one extra instruction. They could've used the WDM instruction as an extension to another set of 256 instructions, and did useful stuff like ALU instructions with index registers, and register-register ALU instructions.


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