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PostPosted: Mon May 27, 2019 7:15 pm 
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In the thread about WDC's uncompleted 32 bit CPU, I started brainstorming about ideas for a 32 bit 65xx processor, but I realize that thread isn't the best place for this, and I had also been busy fleshing it out. Below is the complete instruction set; it's not binary compatible with any 65xx processor, but every instruction (other than 65816 direct page instructions) should be there.

Notable features include:
    32 bit program and data address space
    Individually selectable register sizes (8, 16, 32 bit)
    New Z register (ST0 replaces the 65816's STZ instruction)
    signed and unsigned multiply and divide instructions
    Zero page as on chip cache (no longer mapped to memory)
    Index registers now orthogonal for 32 bit long address instructions
    Other miscellaneous new instructions

Code:
Processor Bits
High:   ZZYYXXAA   ;register size selector (both 10 and 11 are 32bit)
Low:   NV__DIC_



Operand in Word:
   SPH byte      ;set bits in high byte of P
   SPL byte      ;set bits in low byte of P
   RPH byte      ;reset bits in low byte of P
   RPL byte      ;reset bits in low byte of P
   
   LPH byte      ;load high byte of P
   LPL byte      ;load low byte of P
   
   ;only one operand is required (bank byte of addr)
   MVP      ;MVP into zp
   MVP      ;MVP out of zp
   MVN      ;MVN into zp
   MVN      ;MVN out of zp
   
   ;load byte, zero extend to register size
   LAZ #byte
   LXZ #byte
   LYZ #byte
   LZZ #byte
   
   LDA sr,S
   LDA (sr,S)
   LDA (sr,S),Y
   LDA zp
   LDA zp,X
   LDA zp,Y
   LDA zp,Z
   LDA (zp)
   LDA (zp,X)
   LDA (zp),Y
   LDA [zp]
   LDA [zp,X]
   LDA [zp],Y
   
   LDX zp
   LDX zp, Y
   LDX zp, Z
   LDY zp, X
   LDY zp, Z
   LDX zp, Y
   LDX zp, Z
   
   STA sr,S
   STA (sr,S)
   STA (sr,S),Y
   STA zp
   STA zp,X
   STA zp,Y
   STA zp,Z
   STA (zp)
   STA (zp,X)
   STA (zp),Y
   STA [zp]
   STA [zp,X]
   STA [zp],Y
   
   STX zp
   STX zp,Y
   STX zp,Z
   STY zp
   STY zp,X
   STY zp,Z
   STZ zp
   STZ zp,X
   STZ zp,Y
   
   ;equivalent to STZ for the 65816
   ST0 zp
   ST0 zp,X
   ST0 zp,Y
   ST0 zp,Z
   
   ;Warning: INC and DEC are only for addresses; use INA/DEA for A
   INC zp
   INC zp,X
   INC zp,Y
   INC zp,Z
   
   DEC zp
   DEC zp,X
   DEC zp,Y
   DEC zp,Z
   
   ;ommiting an operand will increment/decrement by 1
   INA #byte + 1
   INX #byte + 1
   INX zp
   INY #byte + 1
   INY zp
   INZ #byte + 1
   INZ zp
   
   DEA #byte + 1
   DEX #byte + 1
   DEX zp
   DEY #byte + 1
   DEY zp
   DEZ #byte + 1
   DEZ zp
   
   ;add without carry
   ADD sr,S
   ADD (sr,S)
   ADD (sr,S),Y
   ADD zp
   ADD zp,X
   ADD zp,Y
   ADD zp,Z
   ADD (zp)
   ADD (zp,X)
   ADD (zp),Y
   ADD [zp]
   ADD [zp,X]
   ADD [zp],Y
   
   ADC sr,S
   ADC (sr,S)
   ADC (sr,S),Y
   ADC zp
   ADC zp,X
   ADC zp,Y
   ADC zp,Z
   ADC (zp)
   ADC (zp,X)
   ADC (zp),Y
   ADC [zp]
   ADC [zp,X]
   ADC [zp],Y
   
   ;subtract without carry
   SUB sr,S
   SUB (sr,S)
   SUB (sr,S),Y
   SUB zp
   SUB zp,X
   SUB zp,Y
   SUB zp,Z
   SUB (zp)
   SUB (zp,X)
   SUB (zp),Y
   SUB [zp]
   SUB [zp,X]
   SUB [zp],Y
   
   SBC sr,S
   SBC (sr,S)
   SBC (sr,S),Y
   SBC zp
   SBC zp,X
   SBC zp,Y
   SBC zp,Z
   SBC (zp)
   SBC (zp,X)
   SBC (zp),Y
   SBC [zp]
   SBC [zp,X]
   SBC [zp],Y
   
   AND sr,S
   AND (sr,S)
   AND (sr,S),Y
   AND zp
   AND zp,X
   AND zp,Y
   AND zp,Z
   AND (zp)
   AND (zp,X)
   AND (zp),Y
   AND [zp]
   AND [zp,X]
   AND [zp],Y
   
   EOR sr,S
   EOR (sr,S)
   EOR (sr,S),Y
   EOR zp
   EOR zp,X
   EOR zp,Y
   EOR zp,Z
   EOR (zp)
   EOR (zp,X)
   EOR (zp),Y
   EOR [zp]
   EOR [zp,X]
   EOR [zp],Y
   
   ORA sr,S
   ORA (sr,S)
   ORA (sr,S),Y
   ORA zp
   ORA zp,X
   ORA zp,Y
   ORA zp,Z
   ORA (zp)
   ORA (zp,X)
   ORA (zp),Y
   ORA [zp]
   ORA [zp,X]
   ORA [zp],Y
   
   ;signed multiply (high 32 bits of product is loaded in Z, zero extended)
   MUL zp
   MUL zp,X
   MUL zp,Y
   MUL zp,Z
   
   ;unsigned multiply (high 32 bits of product is loaded in Z, zero extended)
   UMU zp
   UMU zp,X
   UMU zp,Y
   MUL zp,Z
   
   ;signed divide (remainder is loaded in Z, zero extended)
   DIV zp
   DIV zp,X
   DIV zp,Y
   MUL zp,Z
   
   ;unsigned divide (remainder is loaded in Z, zero extended)
   UDI zp
   UDI zp,X
   UDI zp,Y
   MUL zp,Z
   
   ASL zp
   ASL zp,X
   ASL zp,Y
   ASL zp,Z
   LSR zp
   
   LSR zp,X
   LSR zp,Y
   LSR zp,Z
   
   ROL zp
   ROL zp,X
   ROL zp,Y
   ROL zp,Z
   
   ROR zp
   ROR zp,X
   ROR zp,Y
   ROR zp,Z
   
   CMP sr,S
   CMP (sr,S)
   CMP (sr,S),Y
   CMP zp
   CMP zp,X
   CMP zp,Y
   CMP zp,Z
   CMP (zp)
   CMP (zp,X)
   CMP (zp),Y
   CMP [zp]
   CMP [zp,X]
   CMP [zp],Y
   
   CPX zp
   CPY zp
   CPZ zp
   
   BIT zp
   BIT zp,X
   BIT zp,Y
   BIT zp,Z
   
   BRA nearlabel
   BEQ nearlabel
   BNE nearlabel
   BCS nearlabel
   BCC nearlabel
   BVS nearlabel
   BVC nearlabel
   BMI nearlabel
   BPL nearlabel
   
   NOP
   
   WDM
   WDM
   WDM
   WDM
   WDM
   WDM
   WDM
   WDM
   WDM
   WDM
   WDM
   WDM
   WDM
   WDM
   WDM
   WDM
   WDM
   WDM
   WDM
   WDM
   WDM
   WDM
   WDM
   WDM   ;taken
   WDM   ;taken



;Operand Not in Word / No Operand
   PEA
   PEI
   PER
   PHK
   PHB
   PHP
   PHA
   PHX
   PHY
   PHZ
   
   PLB
   PLP
   PLA
   PLX
   PLY
   PLZ
   
   TCS
   TAX
   TAY
   TAZ
   TXA
   TXY
   TXZ
   TYA
   TYX
   TYZ
   TZA
   TZX
   TZY
   
   XWA      ;exchange high and low words of A
   XBA      ;exchange high and low bytes of AL
   XWX      ;exchange high and low words of X
   XBX      ;exchange high and low bytes of XL
   XWY      ;exchange high and low words of Y
   XBY      ;exchange high and low bytes of YL
   XWZ      ;exchange high and low words of Z
   XBZ      ;exchange high and low bytes of ZL
   
   MVP
   MVN
   
   LDA #const
   LDA addr
   LDA addr,X
   LDA addr,Y
   LDA addr,Z
   LDA (addr)
   LDA (addr,X)
   LDA (addr),Y
   LDA [addr]
   LDA [addr,X]
   LDA [addr],Y
   LDA long
   LDA long,X
   LDA long,Y
   LDA long,Z
   
   LDX #const
   LDX addr
   LDX addr,Y
   LDX addr,Z
   LDY #const
   LDY addr
   LDY addr,X
   LDY addr,Z
   LDZ #const
   LDZ addr
   LDZ addr,Y
   LDZ addr,X
   
   STA #const
   STA addr
   STA addr,X
   STA addr,Y
   STA addr,Z
   STA (addr)
   STA (addr,X)
   STA (addr),Y
   STA [addr]
   STA [addr,X]
   STA [addr],Y
   STA long
   STA long,X
   STA long,Y
   STA long,Z
   
   STX addr
   STX addr,Y
   STX addr,Z
   STX long
   STX long,Y
   STX long,Z
   STY addr
   STY addr,X
   STY addr,Z
   STY long
   STY long,X
   STY long,Z
   STZ addr
   STZ addr,X
   STZ addr,Y
   STZ long
   STZ long,X
   STZ long,Y
   
   ST0 addr
   ST0 addr,X
   ST0 addr,Y
   ST0 addr,Z
   ST0 long
   ST0 long,X
   ST0 long,Y
   ST0 long,Z
   
   ADD #const
   ADD addr
   ADD addr,X
   ADD addr,Y
   ADD addr,Z
   ADD (addr)
   ADD (addr,X)
   ADD (addr),Y
   ADD [addr]
   ADD [addr,X]
   ADD [addr],Y
   ADD long
   ADD long,X
   ADD long,Y
   ADD long,Z
   
   ADC #const
   ADC addr
   ADC addr,X
   ADC addr,Y
   ADC addr,Z
   ADC (addr)
   ADC (addr,X)
   ADC (addr),Y
   ADC [addr]
   ADC [addr,X]
   ADC [addr],Y
   ADC long
   ADC long,X
   ADC long,Y
   ADC long,Z
   
   SUB #const
   SUB addr
   SUB addr,X
   SUB addr,Y
   SUB addr,Z
   SUB (addr)
   SUB (addr,X)
   SUB (addr),Y
   SUB [addr]
   SUB [addr,X]
   SUB [addr],Y
   SUB long
   SUB long,X
   SUB long,Y
   SUB long,Z
   
   SBC #const
   SBC addr
   SBC addr,X
   SBC addr,Y
   SBC addr,Z
   SBC (addr)
   SBC (addr,X)
   SBC (addr),Y
   SBC [addr]
   SBC [addr,X]
   SBC [addr],Y
   SBC long
   SBC long,X
   SBC long,Y
   SBC long,Z
   
   NEG      ;negate A (two's compliment)
   
   AND #const
   AND addr
   AND addr,X
   AND addr,Y
   AND addr,Z
   AND (addr)
   AND (addr,X)
   AND (addr),Y
   AND [addr]
   AND [addr,X]
   AND [addr],Y
   AND long
   AND long,X
   AND long,Y
   AND long,Z
   AND #const
   AND addr
   AND addr,X
   AND addr,Y
   AND addr,Z
   AND (addr)
   AND (addr,X)
   AND (addr),Y
   AND [addr]
   AND [addr,X]
   AND [addr],Y
   AND long
   AND long,X
   AND long,Y
   AND long,Z
   
   EOR #const
   EOR addr
   EOR addr,X
   EOR addr,Y
   EOR addr,Z
   EOR (addr)
   EOR (addr,X)
   EOR (addr),Y
   EOR [addr]
   EOR [addr,X]
   EOR [addr],Y
   EOR long
   EOR long,X
   EOR long,Y
   EOR long,Z
   
   ORA #const
   ORA addr
   ORA addr,X
   ORA addr,Y
   ORA addr,Z
   ORA (addr)
   ORA (addr,X)
   ORA (addr),Y
   ORA [addr]
   ORA [addr,X]
   ORA [addr],Y
   ORA long
   ORA long,X
   ORA long,Y
   ORA long,Z
   
   MUL #const
   MUL addr
   MUL addr,X
   MUL addr,Y
   MUL addr,Z
   
   UMU #const
   UMU addr
   UMU addr,X
   UMU addr,Y
   UMU addr,Z
   
   DIV #const
   DIV addr
   DIV addr,X
   DIV addr,Y
   DIV addr,Z
   
   UDI #const
   UDI addr
   UDI addr,X
   UDI addr,Y
   UDI addr,Z
   
   ASL addr
   ASL addr,X
   ASL addr,Y
   ASL addr,Z
   
   LSR addr
   LSR addr,X
   LSR addr,Y
   LSR addr,Z
   
   ROL addr
   ROL addr,X
   ROL addr,Y
   ROL addr,Z
   
   ROR addr
   ROR addr,X
   ROR addr,Y
   ROR addr,Z
   
   CMP #const
   CMP addr
   CMP addr,X
   CMP addr,Y
   CMP addr,Z
   CMP (addr)
   CMP (addr,X)
   CMP (addr),Y
   CMP [addr]
   CMP [addr,X]
   CMP [addr],Y
   CMP long
   CMP long,X
   CMP long,Y
   CMP long,Z
   
   CPX #const
   CPX addr
   CPY #const
   CPY addr
   CPZ #const
   CPZ addr
   
   BIT addr
   BIT addr,X
   BIT addr,Y
   BIT addr,Z
   
   BRL label
   
   JMP addr
   JMP (addr)
   JMP (addr,X)
   JMP [addr]
   JMP [addr,X]
   JMP long
   
   JSR addr
   JSR (addr)
   JSR (addr,X)
   JSR [addr]
   JSR [addr,X]
   JSR long
   
   RTL
   RTS
   RTI


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PostPosted: Mon May 27, 2019 11:35 pm 
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Joined: Fri Nov 12, 2004 2:49 pm
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Location: Chexbres, VD, Switzerland
This is an old idea and there's already a few threads on 6502.org about this.
http://forum.6502.org/viewtopic.php?f=2&t=2919
http://forum.6502.org/viewtopic.php?f=10&t=2681
(not an exhaustive list)


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PostPosted: Fri May 31, 2019 11:43 am 
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Posts: 2900
I think you should do 16-bit operands instead, because I doubt you will ever exceed 65536 instructions with only 4 registers.


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PostPosted: Fri May 31, 2019 1:30 pm 
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Joined: Thu Apr 18, 2019 9:13 am
Posts: 161
Drew Sebastino wrote:
In the thread about WDC's uncompleted 32 bit CPU, I started brainstorming about ideas for a 32 bit 65xx processor, but I realize that thread isn't the best place for this, and I had also been busy fleshing it out. Below is the complete instruction set; it's not binary compatible with any 65xx processor, but every instruction (other than 65816 direct page instructions) should be there.


How would you envision the opcodes for the instructions being laid out? If I were doing a 6502-style processor I'd have 24 instructions use a three-bit field for addressing-mode select, and have all the other instructions use just one, but you have 13 addressing modes but don't allow them to be used with all instructions. If you were to draw opcodes on a 16x16 grid, where would different parts of the instruction set go?


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PostPosted: Sat Jun 29, 2019 2:32 pm 
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Quote:
High: ZZYYXXAA ;register size selector (both 10 and 11 are 32bit)

:cry: :cry: :cry:

Can we get away from the variable size registers concept?

How about more register with different sizes?

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PostPosted: Sat Jun 29, 2019 3:19 pm 
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Oh man, I just read ZZYYXXAA and thought it was a game genie code...

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