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PostPosted: Wed Oct 28, 2015 8:00 pm 
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The SNES APU's BRR gets sixteen samples stored into nine bytes. So

32000 samples/second × 9 bytes/16samples = 18000 bytes/second.


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PostPosted: Wed Oct 28, 2015 9:26 pm 
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Well, even if it does take up that much memory, I imagine you could actually be able to get away with many instruments being half a second long (9000 bytes) and just keep looping it and changing the pitch or something. (Of course, many samples will sound almost exactly the same at a lower sample rate too.) I looked at the Gunforce 2 instruments again (I was trying to look at waveforms and seeing if there was any hope of copying it on the NES) and although the guitar sound kind of loops for whatever reason, (and the pitch is a little higher and it's louder at the beginning), I saw that it fits in a little less than half a second at 20000hz. (Which sounds like the correct speed.) Considering that that's about 2/3 of the highest sample rate on the SNES, if you multiply 9000 by 3/2, you get 13500 bytes, which is a little more than a 5th of audio ram. Although that isn't to astronomically terrible, I'm sure you could also still make the sound effect shorter by shortening the loop or just decreasing the quality by a little. What would have been a great idea for Nintendo would have been to taken 32KB of main ram and put it toward audio ram, and put the other 32KB to vram.

You know though, what's actually so CPU intensive about transferring data to vram? I heard it's that the SPC700 runs at a slower clock speed than the 65816. Because of this, you have to somehow have both chips be in sync with one another, but how do you do this? Anyway, if you try to do this, wouldn't just one write cause you to have to wait for both chips to be in sync again? Does the 65816 not have the option to run at the same clock speed as the SPC700? If so, you'd just turn it on, transfer the data, and then set the speed back to normal again.


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PostPosted: Wed Oct 28, 2015 9:46 pm 
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The thing that is so CPU intensive is that neither the SNES CPU nor the APU CPU have the ability to fire an interrupt in the other.

As a result, there's only a few ways to manage transfers:
* S-CPU writes one to three bytes and a handshake byte, and waits for the A-CPU to write an acknowledgement. The A-CPU waits for the handshake, transfer the data accordingly, and writes an acknowledgement.
* S-CPU writes one to three bytes and a clock byte, assume the other end will keep up. The A-CPU waits for the clock byte to change, then transfers the data accordingly.
* S-CPU/HDMA writes data at a fixed rate and the A-CPU maybe drops it on the floor. (The two CPUs run off entirely disjoint clocks, one of which can and will drift relative to the other, so fixed timing loops become trickier)

Unfortunately, using a timed IRQ to transmit data adds so much overhead to the S-CPU that it's not clear it's worth it.


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PostPosted: Wed Oct 28, 2015 10:09 pm 
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Perhaps the best hope for a rapid transfer is to use a 3+clock loop with an HDMA channel. That doesn't use quite as much S-CPU time as a fully synchronized PIO loop, but the S-CPU has to copy the data from ROM to RAM in order to insert the clock bytes, and the S-SMP has about 64 cycles to stash 3 bytes and wait for next clock.


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