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I don't think it will be as easy.
The YM2413 has far fewer pins than the VRC7 does (just 18 pins total), so I don't believe there is a pin that the debug mode could easily 'hide' behind. However, the YM2413 application manual ( http://www.smspower.org/uploads/Develop ... 2413am.pdf pdf page 6, document page 3) DOES state that there is a debug/test mode involving pins D0 and D1 becoming outputs, if /CS is low(active), /WE is high(inactive) and A0 is low. If, in this mode, D2 thru D7 are still inputs, that means D2-D7 can select between 64 different pairs of bits to be 'visible' on D0 and D1, for 128 bits of internal state visible. The test mode of the VRC7 (described at https://pastebin.com/2gAwGmFT ) gives 40 bits of internal state. Each patch is 64 bits, but the two operators for each channel, modulator and carrier, happen one after the other, so you see only half the data (some of it common for modulator/carrier) for each patch at a time, sequentially for all the channels. (what the exact order is of this data vs the channel number, I'm not sure.)
So 128 bits, if D2-D7 really work that way, is more than enough data to hold not only all 40 bits of the 'current patch state', but also other fun stuff like the current phase count, current envelope count, bits having to do with the envelope position and key-on, etc. Even if it turns out only 64 bits are available, that's still enough for 40 patch bits plus 24 other bits.

Also, for this debug/test mode on the YM2413/OPLL, does changing A0 have any effect? The document seems ti imply that if /CS is low, /WE is high and A0 is high, the data bus is high impedance/disconnected, but this could use testing as well.

LN

_________________
"When life gives you zombies... *CHA-CHIK!* ...you make zombie-ade!"

Some info about VRC7's test register(0x0f):

This info was gathered by analyzing VRC7 die shot and i haven't tested it on hardware so this info might be incorrect. I don't know if this info also can be applied for YM2413.

Also VRC7 has it's own way to test DAC. You need to set VRC7 to debug mode, connect pin 2 to ground and pin 47 to +5v(or vice versa, not 100% sure). Then you just need to write 8 bit sample to VRC7(any port, A0 is ignored)

So I wrote a simple hotswap test (test_vrc7) to verify that theory.

I've attached a recording of the test ROM. It plays a 3 second reference tone, then a series of 8 tones where it's on for 1 second, sets a $0F bit for 1 second, then clears the $0F bit for 1 second, then release. After that it plays 3 tones after toggling bit 1, then 3 tones without doing that to show that it can reset LFO. The test is done twice, once with instrument 10 (demonstrates tremolo), and again with instrument 12 (demonstrates vibrato).

So the observed effects from the recording:

• bit 0 - tone goes very noisy/buzzy (feedback?) and is maybe stuck at full volume (envelope appears to have continued on through this period though, when it resumes it has already fallen to where it should be)
• bit 1 - LFO immediately stops, seems like it's resetting immediately to 0 and not just halting
• bit 2 - Tone goes silent, envelope seems to have continued through.
• bit 3 - With instrument 10 it makes a mild rapid buzz and with instrument 12 it seems like the vibrato is halted (but if it's 1024x speed it's maybe just so fast it sounds flat). By the envelope curve of instrument 10 it looks like the envelope is paused while this bit is set, and does not resume until it is cleared? (Instrument 12 has a flat envelope after 1s so this effect isn't noticeable in the second test.)
• bit 4-7 no effect

Also, toggling bit 1 does indeed seem to reset both LFOs, which is great! Finally a technique that works for that.

Edit: so compared to your description... what does the "next noise bit" mean? And was this maybe attached to bit 0 rather than bit 1 of this $0F register, explaining the buzzy/feedback-style noise? The other 3 seem to correspond to your description validly, though I guess I don't know what the bit 3 function of D2 you described to clock the EG is... but it does seem that EG is effectively halted by it for this test so that seems to corroborate?

Updated my patch_vrc7 hotswap test ROM with a few extra attempts to get the LFOs synchronized, etc. with this new information.

Made a reference recording using the new patch set, in case anyone wants to see/hear how perfect it is. (I'm still kinda shocked by finally having this data!)

http://rainwarrior.ca/projects/nes/patch_vrc7_nukeykt.flac (39MB FLAC)

I was a bit unclear/wrong with bit 0. it just disables EG output and zero attenuation value is sent to operator unit(i.e operator outputs at full volume).
In bit 1 description i meant rhythm mode's noise generator(23 bit LSFR) which doesn't affect melodic channels.
Bit 3 allows to serially input EG timer value, but you need to write it at the rate of MCLK/4, so if don't write anything to it, or write with wrong timing EG will basically stuck.

Oh, the noisiness with bit 0 set is just the modulator being forced to full strength isn't it. Ah, okay.