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PostPosted: Thu Oct 18, 2018 1:52 pm 
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I tried putting a 10k pull-down on each of the unknown pins, and I found the following voltage clues:

  • VCC 5.01V
  • Pin#, Open Voltage, 10k to Gnd voltage

  • 94 (CHR A0), 5.01, 4.96 <- Clearly driven high
  • 74 (PRG /CE), 5.01, 4.97 <- Clearly driven high
  • 70 (PRG RAM A14), 5.01, 4.97 <- Clearly driven high
  • 73 (unknown), 5.01, 4.97 <- Clearly driven high
  • 93 (unknown), 5.01, 4.96 <- Clearly driven high

  • 76 (PRG RAM /WE) 4.96, 3.17
  • 72 (PRG RAM 1 /CE), 4.96, 3.17
  • 71 (PRG RAM 0 /CE), 4.96, 3.17
  • 75 (unknown), 4.96, 3.17

  • 30 (unknown), 5.00, 1.94
  • 29 (unknown), 5.00, 1.93
  • 92 (unknown), 5.00, 1.86
  • 82 (unknown), 5.00, 1.85
  • 81 (unknown), 5.00, 1.72

  • 28 (PPU A13), 4.96, 0.89 <- Input
  • 98 (SL3), 4.99, 0.90V <- Input
  • 97 (CL3), 4.99, 0.90V <- Input

Edit:
verified that DAC is indeed coming out from Pin 2. I characterized the voltage to DAC value here:
https://wiki.nesdev.com/w/index.php/MMC ... .245011.29


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PostPosted: Thu Oct 18, 2018 6:06 pm 
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Ben Boldt wrote:
The CL/SL mode stuff has been on the MMC5 pinout wiki page since its creation
It was just copied from kevtris's documentation here.


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PostPosted: Thu Oct 18, 2018 8:00 pm 
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lidnariq wrote:
Ben Boldt wrote:
The CL/SL mode stuff has been on the MMC5 pinout wiki page since its creation
It was just copied from kevtris's documentation here.

Okay. Where do you think he got that info from? How would he know that it has to do with split-screen scrolling? To me, looking at Just Breed's PCB, all of the jumpers that are closed are labeled CLx and all of them that are open are labeled SLx (where x is a number). It looks like for each x, there is a pair of CLx and SLx always near each other. If CL and SL are to be overall modes of the MMC5, it might shed some light to think about the overall differences when opening all of the CLx and closing all of the SLx -- not just CL3 and SL3.


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PostPosted: Thu Oct 18, 2018 10:55 pm 
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Well, we know by inspection that CL4-6 and SL4-6 connect CHR A0-A2 to PPU A0-A2, or instead go via the MMC5.

And the only known behavior that could use that is the left-and-right split screen. (Or flipping background tiles vertically, but that's evidently not present)

Similarly, we know what SL2/CL2 (battery backup of RAM), SL1/CL1 (battery backup of second RAM), and SL15/CL15 (enables two 32KiB RAMs on NES-ETROM) do.

As to whether Kevtris assumed something, or was citing some even older source ... don't know. You might be able to get in touch with him via IRC.


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PostPosted: Fri Oct 19, 2018 12:17 am 
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lidnariq wrote:
And the only known behavior that could use that is the left-and-right split screen.

Okay, that explains a lot. I admittedly had not even looked at where any of the jumpers connect yet, but I would not have been able to see the relation to split screen anyway. Thanks for your experience on this. So basically, swapping several CLx/SLx pairs appears to be the idea kevtris was already going on, possibly with the same assumptions that I was suggesting.

I guess the pins named CL3 and SL3 are right next to CHR A0, A1, A2, and these 3 address bits point to the split screen business. That does seem a pretty strong indication that they are directly related. In case they aren't, it is easy for me not to get stuck on that relation because I don't understand it anyway! :) I research it with a truly open mind. :P


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PostPosted: Fri Oct 19, 2018 12:56 am 
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Ben Boldt wrote:
I guess the pins named CL3 and SL3 are right next to CHR A0, A1, A2, and these 3 address bits point to the split screen business. That does seem a pretty strong indication that they are directly related. In case they aren't, it is easy for me not to get stuck on that relation because I don't understand it anyway! :)
Unfortunately, they're not. (Much to my disappointment/surprise)

4-6 are vaguely in the middle of the PCB, between CHR and the MMC5.
1 and 2 are next to their corresponding PRG RAM
15 isn't particularly near anything, between PRG ROM and PRG RAM
but 3 is off in the corner near the battery in HVC/NES-E{K/T/W}ROM.

HVC/NES-ELROM might be the exception that led to the impression. On these PCBs 3 is vaguely near 4-6.


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PostPosted: Fri Oct 19, 2018 12:14 pm 
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I think I would like to set up a test that has random PPU addresses, writes and reads, and monitors CHR A0, A1, A2, CL3, SL3, and especially Unknown Pin 93.

I measured the voltages of all pins today with and without a 10k pull-down. Only PRG RAM /CE /WE -related pins do the 3.17V thing measured on pin 75. That is a good clue that 75 relates to those.

73 and 93 act like ordinary output high seen on lots of pins. Our best clues are proximity to other pins. 73 measures like 74 (PRG /CE), also 93 measures like 94/95/96 (CHR A0/A1/A2).

Pins 29, 30, 81, 82, and 92 all have this weird 1.8V business not seen on any known pins. :? It works out to an 18k internal pull-up. It could mean that those pins are related to each other, or it might not be a good sign that those pins actually do anything... But at least 73/75/93 look promising.

I did some more DAC testing and came up with a more general equation that considers AVcc:
Pin 2 Voltage = [(DAC value / 255) * (0.4 * AVcc)] + (0.1 * AVcc)

Attachment:
dac characteristic.png
dac characteristic.png [ 38.98 KiB | Viewed 843 times ]

I updated the Wiki with this.

I keep dreaming about the DAC being able to play by itself out of the MMC5's internal RAM, and then interrupt when done. That would be so cool.


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PostPosted: Fri Oct 19, 2018 12:27 pm 
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If you leave AVcc floating, but supply +5V on DVcc, what voltage appears on AVcc?


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PostPosted: Fri Oct 19, 2018 12:34 pm 
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lidnariq wrote:
If you leave AVcc floating, but supply +5V on DVcc, what voltage appears on AVcc?


And try to measure the internal resistance of that output too.


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PostPosted: Fri Oct 19, 2018 12:46 pm 
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lidnariq wrote:
If you leave AVcc floating, but supply +5V on DVcc, what voltage appears on AVcc?

Flat zero.

krzysiobal wrote:
And try to measure the internal resistance of that output too.

Will do. DACs typically are made out of big resistor networks so I will consider that and test different conditions, etc.

Edit:
It looks to have a current-limited output at about 173 uA:

Attachment:
dac impedance.png
dac impedance.png [ 14.38 KiB | Viewed 817 times ]


I calculate the maximum non-distorted load to be 14.45 kohm to gnd. I am not sure if it hurts it to enter current-limit mode, so I only applied the load momentarily for each point to read the meter, then took it away.

Edit 2:
I have more work to do on this -- The current limit depends on AVcc. The graph shown is with AVcc = 5V. I tried reducing AVcc to 3V and it current limited to 0.720 volts with the 8.03k resistor.

Edit 3:
Attachment:
dac current limit vs. AVcc.png
dac current limit vs. AVcc.png [ 13.21 KiB | Viewed 816 times ]


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PostPosted: Fri Oct 19, 2018 9:19 pm 
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Wait, so the MMC5 DAC is linear? That means it's not just a repackaged APU.

Do you have any plans to measure the pulse channels? I'm not hardware-savvy enough to tell if that's feasible with your setup.


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PostPosted: Sat Oct 20, 2018 8:07 am 
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Rahsennor wrote:
Wait, so the MMC5 DAC is linear? That means it's not just a repackaged APU.

We've known for a long time that the MMC5's pulse channels aren't just a repackaged APU, and the presence of a linear DAC would just be one of the reasons. Another would be the lack of pitch sweeping support (which isn't surprising, because they took up about 1/3 of the RP2A03 pulse channels' die space), and yet another would be the fact that the RP2A03 and MMC5 use inherently different processes (the former is depletion-load NMOS, while the latter is CMOS).

Still, replacing the DAC would've been trivial even if the MMC5 did use a direct copy of the NES APU, since it's only a single isolated component of it - in Visual 2A03, the Pulse DAC is just the region enclosed by t10283 and t10311, and the Triangle/Noise/PCM DAC is just the area within t13792 and t14502.

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PostPosted: Sat Oct 20, 2018 11:17 am 
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Quietust wrote:
MMC5 use inherently different processes [...] while the latter is CMOS
We know it's CMOS?


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PostPosted: Sat Oct 20, 2018 3:10 pm 
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lidnariq wrote:
Quietust wrote:
MMC5 use inherently different processes [...] while the latter is CMOS
We know it's CMOS?

I suppose we technically don't know 100% for certain, so I retract that particular statement.

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PostPosted: Sat Oct 20, 2018 7:32 pm 
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Do we have any insinuation that it's CMOS?

I assumed it was NMOS because inputs source current, so if there's any evidence any direction I'm curious to hear about it.


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