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PostPosted: Wed Sep 18, 2013 7:52 pm 
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Joined: Sun Sep 19, 2004 11:12 pm
Posts: 19122
Location: NE Indiana, USA (NTSC)
In this post, infiniteneslives wrote:
With [extra PRG-RAM] being a motive for people to make the leap to MMC5 it seems like a worthwhile addition. If we were to take it one step further it might be useful to have one of those bits designate a means to put PRG-RAM in $8000-FFFF. Possibly use bit 4 to swap out the last PRG-RAM bank with the ROM bank that is otherwise fixed to the 2nd to last bank? [...] Might be a good idea to use bit 5 to designate the bank in ROM as read only or r/w. ALL of this is back-compatible.

That'd need a new mapper number because existing mapper 4 ROMs may already be writing 1 to bits 4 and/or 5. Just having bits 3-0 control the bank number would be fully backward compatible with the existing 8K definition and wouldn't need a new mapper or NES 2.0 submapper, as those address outputs are just not connected to the RAM on the existing board.

That and I'd like someone with a logic analyzer to see if FME-7 still outputs the bank bits when RAM is enabled in $6000-$7FFF.

To make it clearer what I'm talking about, here's the behavior of mapper 69 (FME-7, Sunsoft 5B):
Code:
7654 3210  Register 8: PRG RAM control
SSxB BBBB
|| | ||||
|| +-++++- Select 8 KiB bank of PRG ROM at $6000-$7FFF
++-------- Chip select: 0: ROM; 1: Open bus; 3: RAM

I'd like to know who can test that B works even when RAM is selected.

And a proposed homebrew extension to mapper 4 (MMC3):
Code:
7654 3210  $A001: PRG RAM control
EWxx BBBB
||   ||||
||   ++++- Select 8 KiB PRG RAM bank at $6000-$7FFF
|+-------- 0: Allow writes to RAM; 1: Read-only
+--------- 0; Disable RAM; 1: Enable RAM


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