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I have a Punch Out cartridge :

Front :


Back :


It didn't work when I bought it
Yesterday I desoldered its PRG and CHR and took them out
I was surprised when I found out that Punch Out is a 256KB game
But as you can see in the pictures the PRG and CHR have only 28pins!
28pins EPROMs like 27C512 can only contain up to 64KB
Anyway I set my Willem EPROM programmer to 27C512 and dumped those PRG and CHR
CHR is OK to some extent and I can see the Punch Out graphic by using TLP
But PRG is severely damaged and that is why the whole cartridge didn't work
Then I noticed that there is an option for 1Mbit (128KB) EPROMs
I used two 29F040 as PRG and CHR then I tested the cartridge with a fresh Punch-Out!! (U) [!] and fortunately it worked!

You know FamiGOD demands sacrifices now and then, so here it goes, may FamiGOD accept it :

Front :


Back :


Is it possible to convert these TTLs to FPGA or CPLD?
If so which one is better to use?
And what part number should I use?

Is it possible to add some more TTLs to make MMC4?

Interesting... sometimes we see pirate carts with discrete logic implementations of moderately complex mappers. I believe we've seen one more complex than the MMC2, but I don't remember which one.


Nintendo has always used 28-pin 128KB mask ROMs for PRG though (128KB CHR needs more pins).

Nice find. Who'll be the first to convert this to a schematic?


It's possible, but you can probably just switch around a couple of the address outputs from the existing TTLs. Another option if you want to reproduce a Fire Emblem or Famicom Wars hack is MMC4 on CPLD from infiniteneslives.com. (Or does the embargo interfere?)

Wow, this is very cool. Only 13 chips to emulate an entire MMC2 with all it's auto-bankswitching features, that's not too bad !

Indeed! My real goal is Fire Emblem!
But I want to make it myself because it is more fun.


Yeah, we are really under pressure from it


Are you sure it is entire?!
Then where is the phi2?

As a guess, right now, somewhere on the PCB there's an OR gate (74'32) that generates the signal (CPU_A14 OR CPU_A13), which needs to become just CPU_A14. Additionally, the PRG bank register is going to be connected to PRG A13 ... A16, and for MMC4 it needs to be PRG A14 ... A17 and CPU A13 needs to connect directly to PRG A13. Finally, you'll need a 74'20 or something to add a RAM.

I'll sit down later and trace out a schematic. Right now I see a 74'75 (4 bits), a 74'175 (4 bits), two 74'670s (32 bits), and a 74'74 (2 bits), I bet the two '670s are used for the CHR banking, and the 74'74 is used for the CHR rendering side, so I guess the other two quad latches must be used for PRG banking and Mirroring control.

Finished tracing everything, but haven't yet started transcribing to a schematic. I did notice one funny thing: the left pattern table (0xxx) uses a different decision criterion for whether it should swap pattern tables. The right pattern table only switches based on PPU A12 .. A3, but the left additionally requires that it fetch from the first row of the pattern, i.e. it requires that PPU A2..A0 is 0. This means that if tile FD and FE were in the same row, when from the left pattern table it would only show a single scanline from the FD bank, but the right pattern table would show eight scanlines.

I have no idea if this is the same as the actual MMC2.

I seem to recall seeing this same detail in the MMC2 patent, though I'm not sure if the real chip behaves the same way.

_________________
Quietust, QMT Productions
P.S. If you don't get this note, let me know and I'll write you another.

Seems that Punch Out puts sprites on the left table and backgrounds on the right.

_________________
Here come the fortune cookies! Here come the fortune cookies! They're wearing paper hats!

Here you go. Eagle SCH, LBR for the split version of the 74'75, PDF, and the png here. It's possible I've made a few mistakes, but mostly the layout just kinda sucks.

The 74'75 input and 74'670 inputs that I've connected nothing to actually do float. The unused AND and OR gates' inputs float too. I was too lazy to draw the connections to the ROMs, though.

I'm not certain how applicable this is; I understand the 74'670 is not terribly easy to come across anymore.

Btw, I asked BootGod to test: the MMC2 does behave according to both the patent and the discretes implementation here. By which I mean, fetches from the left pattern table only trigger on the first row.

I have a MMC5 with only TTL chips.

And any picture?

Pics or it didn't happen

Yep, I'll get some done up and post them later. It's from a Doki Doki Panic pirate cart.