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 Post subject: Re: RAMBO-1 IRQ timing
PostPosted: Tue Feb 04, 2014 11:56 pm 
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You shouldn't forget that NES CPU uses 6502 core. In original, MOS6502 uses 2 input clock signals with same frequency and different phase. And for data strobe signal it has DBE pin, that actually is clock phase 2 signal.
Image
That's why "2". But I don't know why "M" and not "DBE". Because "M2" acts same as MOS6502's "DBE".


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 Post subject: Re: RAMBO-1 IRQ timing
PostPosted: Wed Feb 05, 2014 7:03 am 
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M2 means "Modified Phi2" as far as I can tell. It rises slightly earlier, after the end of TADS but before Phi2 rises, to allow use of slower ROMs.


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 Post subject: Re: RAMBO-1 IRQ timing
PostPosted: Wed Feb 05, 2014 7:38 am 
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lidnariq wrote:
Without telling us what specific thing you're confused by, it's very difficult to make it clearer.

I'm not even clear where you got "Odd and even clocks" from.


OK, from the wiki: "Every cycle on 6502 is either a read or a write cycle". Well, 0, 2, 4, 6, 8 even CPU clock cycles; 1, 3, 5, 7, 9 odd CPU clock cycles.


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 Post subject: Re: RAMBO-1 IRQ timing
PostPosted: Wed Feb 05, 2014 8:19 am 
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Zepper wrote:
lidnariq wrote:
Without telling us what specific thing you're confused by, it's very difficult to make it clearer.

I'm not even clear where you got "Odd and even clocks" from.


OK, from the wiki: "Every cycle on 6502 is either a read or a write cycle". Well, 0, 2, 4, 6, 8 even CPU clock cycles; 1, 3, 5, 7, 9 odd CPU clock cycles.


What the wiki page is meaning to say is that there are no bus-idle cycles. On every single cycle, the bus will be asked to do a read or a write, but not necessarily alternating between the two.


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 Post subject: Re: RAMBO-1 IRQ timing
PostPosted: Wed Feb 05, 2014 11:26 am 
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Don't try to deconstruct it, please. For all it matters, whatever the CPU reads/writes, it does 1 cycle. Now I'm upset. Since 1998, the beginning of my NES emulation things, I know the CPU meanings in emulation terms. If I got it wrong, so tell ALL the others now that they're wrong too. :evil:

Even the CPU instuction timing brings integer numbers, of CPU cycles per instruction (like 3, 4, 5...). How you don't understand OR not allowed to say even/odd cycles? HOW?


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 Post subject: Re: RAMBO-1 IRQ timing
PostPosted: Wed Feb 05, 2014 11:53 am 
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I'm not saying you aren't allowed to think of it however you want, it's just that I haven't the foggiest idea what you mean by odd/even.
Maybe this will help me understand? Say you had the following sequence of instructions:
Code:
LDA #1 ; 2 cycles
LDX 2  ; 3 cycles
LDY #3 ; 2 cycles
Where are the odd and even cycles? Or does it depend on something else that's not visible here? If so, what?


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 Post subject: Re: What is M2?
PostPosted: Wed Feb 05, 2014 12:35 pm 
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Odd and even half cycles. Each CPU cycle consists of a low Phi2 phase followed by a high Phi2 phase. M2 rises sometime near the end of the low Phi2 phase to give the PRG ROM extra time to respond compared to just using Phi2 to calculate PRG ROM /CE.


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 Post subject: Re: RAMBO-1 IRQ timing
PostPosted: Wed Feb 05, 2014 1:02 pm 
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lidnariq wrote:
I'm not saying you aren't allowed to think of it however you want, it's just that I haven't the foggiest idea what you mean by odd/even.
Maybe this will help me understand? Say you had the following sequence of instructions:
Code:
LDA #1 ; 2 cycles
LDX 2  ; 3 cycles
LDY #3 ; 2 cycles
Where are the odd and even cycles? Or does it depend on something else that's not visible here? If so, what?


Do you know what is "PPU frame"? Probably not.


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 Post subject: Re: RAMBO-1 IRQ timing
PostPosted: Wed Feb 05, 2014 1:43 pm 
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Zepper wrote:
Do you know what is "PPU frame"?
Here are the things that I can think of that could remotely plausibly be called even/odd in the NTSC NES:
  • φ1 vs φ2 cycles in the CPU.
  • The phase of the APU, since the APU is mostly clocked at CPU/2.
  • The phase of the read/write cycle for the OAM DMA unit
  • Whether there are a total of 89342 or 89341 total pixels displayed by the PPU on any given field
Is this any of those?


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 Post subject: Re: What is M2?
PostPosted: Wed Feb 05, 2014 6:13 pm 
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I was mentioning the PPU case of even/odd frames (there's a test ROM available), but I gave up because you would question me about the "PPU frame", so I was lost in a reply. At anyway, it's the simplest thing ever: if a instruction takes 3 cycles, we have even/odd/even cycles. Regarding the APU, yes, that's a good approach.


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 Post subject: Re: What is M2?
PostPosted: Wed Feb 05, 2014 7:40 pm 
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Zepper wrote:
if a instruction takes 3 cycles, we have even/odd/even cycles.
Can that sometimes be odd/even/odd ? Or is it always referenced to the start of each instruction?


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 Post subject: Re: What is M2?
PostPosted: Wed Feb 05, 2014 7:49 pm 
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It can be either way. But once you get into 4-cycle instructions, you start to include STA $4014, after which the OAM DMA unit will wait for the correct phase of the DMA clock (half the CPU clock, and I'm assuming it's related to the APU clock) to start.


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 Post subject: Re: RAMBO-1 IRQ timing
PostPosted: Thu Feb 06, 2014 11:50 am 
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HardWareMan wrote:
You shouldn't forget that NES CPU uses 6502 core. In original, MOS6502 uses 2 input clock signals with same frequency and different phase. And for data strobe signal it has DBE pin, that actually is clock phase 2 signal.
(image snipped)
That's why "2". But I don't know why "M" and not "DBE". Because "M2" acts same as MOS6502's "DBE".


That sounded a bit off to me so I dug up a PDF of MOS(CSG)'s Nov 1985 datasheet. Firstly the 650x line of CPUs have a single clock input called Phi0. From this PHi1 and Phi2 are generated, used internally and output. Data Bus Enable (DBE) is:
MOS Technologies/Commodore Semiconductor Group wrote:
Data Bus Enable(DBE)
This TTL compatible input allows external control of the tri-state data output buffers and will enable the microprocessor bus driver when in high state. In normal operation DBE would be driven by the phase two (Phi2) clock, thus allowing data output from microprocessor only during Phi2. During the read cycle, the data bus drivers are internally disabled, becoming essentially an open circuit. To disable data bus drivers externally, DBE should be held low.


The 651x line (not including the 6510) did have Phi1 and Phi2 inputs but still have a Phi2 output.

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 Post subject: Re: What is M2?
PostPosted: Thu Feb 06, 2014 12:18 pm 
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tepples wrote:
It can be either way. But once you get into 4-cycle instructions, you start to include STA $4014, after which the OAM DMA unit will wait for the correct phase of the DMA clock (half the CPU clock, and I'm assuming it's related to the APU clock) to start.

I started referring to the DMA 'clock behavior' as "read/write drumbeat" because I got sick of trying to remember whether the read or write occurred on what was arguably arbitrarily the "odd" or "even" CPU cycle. It's not like the 6502 has an internal cycle counter that starts at 0 [even] or 1 [odd] anyway, so it's silly to impart oddness or evenness on something only humans count. I don't really care whether the DMA drumbeat starts with a read or a write, but my guess would be a read since if nothing's been read then writing would be useless. I also showed in this thread that the APU DMC DMA, which is a single read, occurs in the read of the read/write DMA drumbeat, and that the write is replaced by a read, since writing the APU DMA sample to the PPU would not be appropriate.

In the same vein it seems silly to refer to the different-length PPU frames as odd and even. "short" and "long" perhaps.


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 Post subject: Re: What is M2?
PostPosted: Thu Feb 06, 2014 2:51 pm 
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cpow wrote:
It's not like the 6502 has an internal cycle counter that starts at 0 [even] or 1 [odd] anyway

Technically, the 2A03's APU circuitry does, and the reset pin does initialize it to a known state (though I don't recall which one that is).

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