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 Post subject: Re: RAMBO-1 IRQ timing
PostPosted: Thu Feb 06, 2014 7:46 pm 
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Hojo_Norem wrote:
HardWareMan wrote:
You shouldn't forget that NES CPU uses 6502 core. In original, MOS6502 uses 2 input clock signals with same frequency and different phase. And for data strobe signal it has DBE pin, that actually is clock phase 2 signal.
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That's why "2". But I don't know why "M" and not "DBE". Because "M2" acts same as MOS6502's "DBE".


That sounded a bit off to me so I dug up a PDF of MOS(CSG)'s Nov 1985 datasheet. Firstly the 650x line of CPUs have a single clock input called Phi0. From this PHi1 and Phi2 are generated, used internally and output. Data Bus Enable (DBE) is:
MOS Technologies/Commodore Semiconductor Group wrote:
Data Bus Enable(DBE)
This TTL compatible input allows external control of the tri-state data output buffers and will enable the microprocessor bus driver when in high state. In normal operation DBE would be driven by the phase two (Phi2) clock, thus allowing data output from microprocessor only during Phi2. During the read cycle, the data bus drivers are internally disabled, becoming essentially an open circuit. To disable data bus drivers externally, DBE should be held low.


The 651x line (not including the 6510) did have Phi1 and Phi2 inputs but still have a Phi2 output.

You're right about 6502, but wrong about 650x family.
Image
Maybe you should start to use more original document?
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