nesdev.com
http://forums.nesdev.com/

What is M2?
http://forums.nesdev.com/viewtopic.php?f=9&t=10984
Page 1 of 3

Author:  Zepper [ Thu Sep 05, 2013 3:25 pm ]
Post subject:  What is M2?

In this post, infiniteneslives wrote:
I verified that by leaving M2 low while writing to the mapper

What is M2?

Author:  infiniteneslives [ Thu Sep 05, 2013 3:36 pm ]
Post subject:  Re: RAMBO-1 IRQ timing

Aka phi2, CPU clock.

Author:  Zepper [ Sat Sep 07, 2013 9:59 am ]
Post subject:  Re: RAMBO-1 IRQ timing

infiniteneslives wrote:
Aka phi2, CPU clock.


Odd and even clocks?

Author:  infiniteneslives [ Sat Sep 07, 2013 10:28 am ]
Post subject:  Re: RAMBO-1 IRQ timing

Zepper wrote:
infiniteneslives wrote:
Aka phi2, CPU clock.


Odd and even clocks?


Yeah, every CPU cycle. Falling edges of M2/phi2 defines the end of one cycle and beginning of the next.

The mmc1 basically keeps track of what the last cycle was, if it was a write cycle, then it doesnt allow writes to the shift register. It only allows writes if the last cycle was a read cycle. That's why the garbage writes of RMW instructions is the one that gets latched, and the actual write that follows is ignored.

Author:  Zepper [ Sat Sep 07, 2013 7:40 pm ]
Post subject:  Re: RAMBO-1 IRQ timing

It should be "odd then even cycles", or xx1->xx0, correct?

Author:  infiniteneslives [ Sat Sep 07, 2013 8:21 pm ]
Post subject:  Re: RAMBO-1 IRQ timing

Zepper wrote:
It should be "odd then even cycles", or xx1->xx0, correct?


I'm not 100% sure what you're saying...

It's EVERY CPU cycle. Not sure how to be more clear than that.

I really don't know what an odd vs even CPU cycle is... Are you defining odd vs even based on the program counter (PC) being odd/even? If so, my answer is still no. I think it's safe to say mappers never know if it's an even/odd CPU cycle.

Perhaps the even/odd confusion is coming from the '2' in M2 (aka phi2). The '2' doesn't mean even. '2' is just a label. phi1 is some other clock that I can't recall off hand.

Author:  lidnariq [ Sat Sep 07, 2013 8:23 pm ]
Post subject:  Re: RAMBO-1 IRQ timing

φ1 and φ2 are active-high signals that denote the "internal processing half" and "external bus half" of 6502 activity. They're the logical inversion of each other. No even/odd to it, though.

Author:  ulfalizer [ Sun Sep 08, 2013 5:27 am ]
Post subject:  Re: RAMBO-1 IRQ timing

Each cycle has a φ1 and a φ2, of equal length. The φ1 half-cycle occurs while the input clock is low, the φ2 half-cycle while it is high. They do not span a full cycle, if that's where you got even/odd from.

http://wiki.nesdev.com/w/index.php/CPU_ ... escription was updated recently and covers it too.

Author:  koitsu [ Sun Sep 08, 2013 10:31 am ]
Post subject:  Re: RAMBO-1 IRQ timing

ulfalizer wrote:
http://wiki.nesdev.com/w/index.php/CPU_pin_out_and_signal_description was updated recently and covers it too.

If you're referring to my recent 2 updates: those were in response to the bottom half of this blog post (FYI: Japanese, and Google Translate is not sufficient here). Basically the post consists of a very intelligent guy (see his blog; he does all kinds of hardware work on Famicom stuff) questioning the pinout being called M2 rather than φ2/phi2, and noted that someone's excessive OCD with fraction symbols in fonts made it very hard for him to read the text clearly (apparently some Japanese computers/setups print gobbledegook for those glyphs). But by the end of the post answers his own question (sort of; he concludes that someone likely called it M2 because of familiarity with the Z80 CPU's "M1" pin (not functionality, but the naming convention)). He had other complaints as well -- I had to get my neighbour (who does professional Jap/Eng translation for Nikon) to help me understand what all was being said. My edit was done to clean all this up and more; refer to the diff.

If you were referring to older updates, then ignore what I said above. :-)

Author:  tepples [ Sun Sep 08, 2013 10:48 am ]
Post subject:  Re: RAMBO-1 IRQ timing

koitsu wrote:
But by the end of the post answers his own question (sort of; he concludes that someone likely called it M2 because of familiarity with the Z80 CPU's "M1" pin (not functionality, but the naming convention)).

I was under the impression that M stood for "modified". If there is a connection to the Z80, I wonder how to phrase that most clearly.

Author:  lidnariq [ Sun Sep 08, 2013 11:25 am ]
Post subject:  Re: RAMBO-1 IRQ timing

I'd arbitrarily guess that the M in M2 stands for "memory".

I really doubt it has anything in common with Z80 parlance, where there are a family of different memory access timings (M1 through M5, at least) corresponding to different parts of instruction execution.

Author:  Zepper [ Mon Sep 09, 2013 9:46 am ]
Post subject:  Re: RAMBO-1 IRQ timing

Technical terminology isn't friendly for reading. So, I'd like to suggest what Disch did with his texts - something readable by everyone.

Author:  lidnariq [ Mon Sep 09, 2013 10:37 am ]
Post subject:  Re: RAMBO-1 IRQ timing

Without telling us what specific thing you're confused by, it's very difficult to make it clearer.

I'm not even clear where you got "Odd and even clocks" from.

Author:  ulfalizer [ Tue Sep 10, 2013 12:14 am ]
Post subject:  Re: RAMBO-1 IRQ timing

koitsu wrote:
ulfalizer wrote:
http://wiki.nesdev.com/w/index.php/CPU_pin_out_and_signal_description was updated recently and covers it too.

If you're referring to my recent 2 updates: those were in response to the bottom half of this blog post (FYI: Japanese, and Google Translate is not sufficient here). Basically the post consists of a very intelligent guy (see his blog; he does all kinds of hardware work on Famicom stuff) questioning the pinout being called M2 rather than φ2/phi2, and noted that someone's excessive OCD with fraction symbols in fonts made it very hard for him to read the text clearly (apparently some Japanese computers/setups print gobbledegook for those glyphs). But by the end of the post answers his own question (sort of; he concludes that someone likely called it M2 because of familiarity with the Z80 CPU's "M1" pin (not functionality, but the naming convention)). He had other complaints as well -- I had to get my neighbour (who does professional Jap/Eng translation for Nikon) to help me understand what all was being said. My edit was done to clean all this up and more; refer to the diff.

If you were referring to older updates, then ignore what I said above. :-)


I remember clarifying φ1/2 recently, but might be misremembering. Maybe it was in the Visual Circuit Tutorial. :?

Author:  ulfalizer [ Tue Sep 10, 2013 12:16 am ]
Post subject:  Re: RAMBO-1 IRQ timing

If you're counting in half-cycles, φ1 would be even half-cycles and φ2 odd half-cycles. That seems like a weird way to think about it though. φ1 is just the first part of the CPU cycle and φ2 the second.

Page 1 of 3 All times are UTC - 7 hours
Powered by phpBB® Forum Software © phpBB Group
http://www.phpbb.com/