MMC3 on CPLD

Discuss hardware-related topics, such as development cartridges, CopyNES, PowerPak, EPROMs, or whatever.

Moderators: B00daW, Moderators

User avatar
FARID
Posts: 499
Joined: Wed Apr 07, 2010 1:14 am
Location: Iran
Contact:

MMC3 on CPLD

Post by FARID » Wed Mar 26, 2014 6:29 am

I want to make the MMC3 mapper on CPLD (XC9572)
On the first step I tried to make the first part of CHR bank switching

Here what I did so far :
I used a nand to decode CPU R/W, /ROMSEL, CPU A14, CPU A13, CPU A0 to generate a clock signal right on the STA $8000
Then I used a 74HC161 to latch the command number
Then I used a 74HC138 to decode the command number
Based on the output of the 138 buffers latch PPU A10 / PPU A11 / PPU A12 to make available the needed block of VRAM

Decoding 8000 (100xxxxxxxxxxxx0) :
CPU R/W = 0
A15 = 1 , PHI2 = 1 --> /ROMSEL = 0
A14 = 0
A13 = 0
A0 = 0

Latching 8KB VRAM (PPU) :
2KB VRAM --> $8000 (XXXX X000)
PPU A10 = CHR A10
PPU A11 = 0
PPU A12 = 0

2KB VRAM -->$8000 (XXXX X001)
PPU A10 = CHR A10
PPU A11 = 1
PPU A12 = 0

1KB VRAM --> $8000 (XXXX X010)
PPU A10 = 0
PPU A11 = 0
PPU A12 = 1

1KB VRAM --> $8000 (XXXX X011)
PPU A10 = 1
PPU A11 = 0
PPU A12 = 1

1KB VRAM --> $8000 (XXXX X100)
PPU A10 = 0
PPU A11 = 1
PPU A12 = 1

1KB VRAM --> $8000 (XXXX X101)
PPU A10 = 1
PPU A11 = 1
PPU A12 = 1

Am I on the right direction?
Attachments
02.PNG
01.PNG

User avatar
Quietust
Posts: 1597
Joined: Sun Sep 19, 2004 10:59 pm
Contact:

Re: MMC3 on CPLD

Post by Quietust » Wed Mar 26, 2014 10:44 am

The value you write to $8000 determines which actual bank register gets updated when you write to $8001, and those various bank registers are chosen based on the PPU address lines going into the PPU (whereas your schematic seems to show it using the value written to $8000).
Quietust, QMT Productions
P.S. If you don't get this note, let me know and I'll write you another.

User avatar
FARID
Posts: 499
Joined: Wed Apr 07, 2010 1:14 am
Location: Iran
Contact:

Re: MMC3 on CPLD

Post by FARID » Wed Mar 26, 2014 12:52 pm

This is a simple CHR Bank Switch :

LDA #$00 --> Command number
STA $8000 --> Selects 2 * 1KB VROM page at PPU 0000
LDA #$78 --> CHR bank number
STA $8001 --> Load 800h block of CHR (From 1E000 to 1E800) to PPU (From 0000 to 0800)

I don't know how to split and select VROM page (STA $8000), someone help me please.

tepples
Posts: 22049
Joined: Sun Sep 19, 2004 11:12 pm
Location: NE Indiana, USA (NTSC)
Contact:

Re: MMC3 on CPLD

Post by tepples » Wed Mar 26, 2014 1:02 pm

First you'll want to implement the Namco 108 family (mapper 206 and friends) because it's simpler. Then you can add the extra MMC3 logic (mirroring switch, WRAM decoding, IRQ, etc.) once you have that working.

In any case, for N108 family functionality, you'll need a few dozen D flip-flops for eight bank numbers. $8000 bits 0-2 select which flip-flop to write to, controlling a decoder attached to the flip-flops' load inputs. $8001 writes to the selected flip-flop. Then you use muxes selected by PPU A12-A10 to select whether flip-flops associated with register 0, 1, 2, 3, 4, or 5 control CHR A15-A10 (or A17-A10 for MMC3).

User avatar
FARID
Posts: 499
Joined: Wed Apr 07, 2010 1:14 am
Location: Iran
Contact:

Re: MMC3 on CPLD

Post by FARID » Wed Mar 26, 2014 2:03 pm

Thanks for the info but I really need the answer for this :
How is the 8KB VRAM page of PPU selected?
Can I just hijack its high address lines (PPU A12, A11, A10) just similar to CHR-ROM?
I am talking about right at the STA $8000 for selecting the VRAM page
How does PPU know what address is going to fill in? 0000 or 1000 ... 2000

User avatar
HardWareMan
Posts: 206
Joined: Mon Jan 01, 2007 11:12 am

Re: MMC3 on CPLD

Post by HardWareMan » Sun Mar 30, 2014 7:50 am

Image

User avatar
FARID
Posts: 499
Joined: Wed Apr 07, 2010 1:14 am
Location: Iran
Contact:

Re: MMC3 on CPLD

Post by FARID » Sun Mar 30, 2014 9:04 am

@ HardWareMan
This is awesome!
Did you test it?
How many macrocells does it need?

User avatar
HardWareMan
Posts: 206
Joined: Mon Jan 01, 2007 11:12 am

Re: MMC3 on CPLD

Post by HardWareMan » Sun Mar 30, 2014 7:33 pm

I did my own implementation. I'm using Altera and not Xilinx. But in general, the scheme is taken from someone's working draft of a project, maybe even PowerPack. You should remember this: MMC3 on this scheme contain 6 8-bit CHR registers (used only 7 bit of each register) and 2 6-bit PRG registers. Also it require about 15 registers for IRQ. Every single bit uses 1 CPLD's register.

User avatar
infiniteneslives
Posts: 2100
Joined: Mon Apr 04, 2011 11:49 am
Location: WhereverIparkIt, USA
Contact:

Re: MMC3 on CPLD

Post by infiniteneslives » Sun Mar 30, 2014 10:50 pm

The full blown MMC3 requires over 100 macrocells. Somewhere around 120 depending on the implementation.
FARID wrote:Thanks for the info but I really need the answer for this :
How is the 8KB VRAM page of PPU selected?
Can I just hijack its high address lines (PPU A12, A11, A10) just similar to CHR-ROM?
I am talking about right at the STA $8000 for selecting the VRAM page
How does PPU know what address is going to fill in? 0000 or 1000 ... 2000
I'm not sure if I understand your question, but the CHR-RAM and CHR-ROM implementation of the mmc3 is the same. The PPU has no idea what's going on with the MMC3. It just reads from the addresses it normally does when rendering and the MMC3 switches things around behind the scenes with respect to the PPU. The mmc3 is a slave to the CPU.
If you're gonna play the Game Boy, you gotta learn to play it right. -Kenny Rogers

User avatar
FARID
Posts: 499
Joined: Wed Apr 07, 2010 1:14 am
Location: Iran
Contact:

Re: MMC3 on CPLD

Post by FARID » Mon Mar 31, 2014 12:13 am

@ HardWareMan
Thank you

@ infiniteneslives
I am talking about the VRAM which is inside of the PPU, not CHR-RAM
Am I saying the wrong name?

User avatar
infiniteneslives
Posts: 2100
Joined: Mon Apr 04, 2011 11:49 am
Location: WhereverIparkIt, USA
Contact:

Re: MMC3 on CPLD

Post by infiniteneslives » Mon Mar 31, 2014 12:22 am

FARID wrote:@ infiniteneslives
I am talking about the VRAM which is inside of the PPU, not CHR-RAM
Am I saying the wrong name?
That's what I figured. People typically call it VRAM on the famicom, but it's still ambiguous IMO. Although VRAM (aka CIRAM, aka NT/AT RAM) isn't inside the PPU, it's on the main board though. But you mention 8KB.. VRAM/CIRAM is 2KB. CHR-RAM is typically 8KB, that's why I thought you might have been asking about CHR-RAM.

I believe your question is actually to do with mirroring control. Although I still don't understand your question. There isn't really anything too special about the MMC3's method of mirroring control compared to other ASIC mappers with switchable mirroring. The mapper controls mirroring with the VRAM/CIRAM A10 pin.
If you're gonna play the Game Boy, you gotta learn to play it right. -Kenny Rogers

User avatar
FARID
Posts: 499
Joined: Wed Apr 07, 2010 1:14 am
Location: Iran
Contact:

Re: MMC3 on CPLD

Post by FARID » Mon Mar 31, 2014 1:41 am

Look that this (Page 16) :
Nintendo Entertainment System Documentation v1.0 by Patrick Diskin

It says :
The PPU has its own memory, known as VRAM (Video RAM). Like the CPU, the PPU can also address 64 KB of memory although it only has 16 KB of physical RAM ....

I said 8KB because I am referring to the pattern table area from $0000 ~ $1FFF
I want to know how can I split that area?

User avatar
infiniteneslives
Posts: 2100
Joined: Mon Apr 04, 2011 11:49 am
Location: WhereverIparkIt, USA
Contact:

Re: MMC3 on CPLD

Post by infiniteneslives » Mon Mar 31, 2014 2:40 am

Sounds like you're mixing things up. That doc is okay for some light reading and gaining basic understanding of the NES.
It says :
The PPU has its own memory, known as VRAM (Video RAM).
Yes, true. Like I said though that RAM is on the main board, not inside the PPU.
Like the CPU, the PPU can also address 64 KB of memory
FALSE, the PPU has no A14 nor A15. The PPU can only address 16KBYTE of memory.
although it only has 16 KB of physical RAM ....
Also FALSE. Well perhaps just bad notation. The NES has 2KB (BYTES) of VRAM/CIRAM which is 16Kb (bits). They improperly used big B instead of small b..

I recommend the wiki as a more solid reference.
I said 8KB because I am referring to the pattern table area from $0000 ~ $1FFF
I want to know how can I split that area?
And now you're talking about CHR-RAM on the cartridge which is used for Pattern Tables. You're not talking about VRAM/CIRAM on the NES main board which that doc is talking about. VRAM/CIRAM on the NES main board is used for Name and Attribute Tables. Cartridge CHR-RAM/ROM is used for Pattern Tables.

In any event you want to have 1KB bankswitching, so the mapper will have to control CHR A10 and up. That's the high level answer to your question.
If you're gonna play the Game Boy, you gotta learn to play it right. -Kenny Rogers

User avatar
FARID
Posts: 499
Joined: Wed Apr 07, 2010 1:14 am
Location: Iran
Contact:

Re: MMC3 on CPLD

Post by FARID » Mon Mar 31, 2014 4:59 am

@ infiniteneslives
Thank you for clarification
People says something about official docs!
Where are these official docs?
Can you introduce me some up to date and reliable source? (other than wiki)

tepples
Posts: 22049
Joined: Sun Sep 19, 2004 11:12 pm
Location: NE Indiana, USA (NTSC)
Contact:

Re: MMC3 on CPLD

Post by tepples » Mon Mar 31, 2014 6:30 am

The official Famicom docs are in Japanese, and the translations Nintendo provided to licensed developers were horrid. A lot of developers outside Japan ended up relying on reverse engineering to figure out how the PPU worked. (Source: posts by Andrew Davie, who worked on The Three Stooges, to the nesdev Yahoo! Group) Besides, I don't think anyone here has the legal right to distribute copies of the official docs to the public.

Post Reply