If your ppu is non rev that's prolly the issue, rev A pal ppu seems to be more compatible.
I need to look to see if i have a non rev i can get to Kev for testing.
I have just opened up my third PAL NES and there was no REV A chip inside!
So if you need a RP2C07-0 for testing let me know and I'll ship one over to you
if it isn't too expensive
(I checked, I think it will be cheap enough for me to forget about it).
It's not just the red kits, it's certain PAL ppu chips, rp2c07-0 revs seem to be the worst. Adding a .1uF cap on the ppu clock pin to gnd seems to help a lot, but we'll get Kevtris to look at it closer.
I was recently reading this
and saw in the notes section about how the clock cycles differ between NTSC and PAL CPU/PPUs...
* On NTSC systems, the PPU divides the master clock by 4 while the CPU uses the master clock divided by 12. Since both clocks are fed off the same master clock, this means that there are exactly three PPU ticks per CPU cycle, with no drifting over time (though the clock alignment might vary depending on when you press the Reset button).
* On PAL systems, the PPU divides the master clock by 5 while the CPU uses the master clock divided by 16. As a result, there are exactly 3.2 PPU ticks per CPU cycle.
Forgive me for asking, but does the Hi-Def NES account for the different CPU & PPU clock cycles for a PAL system? I'm assuming it does, but thought I would ask.