I've got mine! Since seller does not give any source I've made some reverse engineering. WIP:
It contains a UA6527 clone of 2A03 NTSC CPU, IS61C256 32K bytes RAM (only 2K bytes are used), Altera Cyclone II EP2C5T144C8N as PPU with TV/VGA RGB output capabilities, Altera MAX3000A CPLD EPM3064ATC100 as logic (74x139 + 74x368 + master clock divider for PPU and PAL/NTSC coder). Also it contain Sony CXA2075M as NTSC coder (NTSC mode hardwired) and RGB output buffer. All video outputs are 75 Ohm. At last, it contain a MM1454 virtual surround processor in hardwired bypass mode (it also can work as Dolby Pro Logic decoder) in sound path. Square and triangle_noise_DPCM channels are not mixed and goes to 3mm jack separatly through MM1454.
Seller disable CPLD JTAG interface, so I replace this CPLD with new one and make simple project. And all works perfectly!
FPGA PPU require 2 frequencies:
A 10,7386MHz (master clock 21,4772MHz/2) as pixel clock for VGA mode (it goes to regular IO pin not dedicated CLK input).
A 5,3693MHz (master clock 21,4772MHz/4) as pixel clock for PPU core. There 2 of this clocks with different phases. And if second phase are not correct, PPU shows corrupted sprites. These 2 phases goes to dedicated clock inputs.
FPGA make 24 bit RGB output that connected to ADV7125 triple video DAC. There is 6 dip switches which marked as: CARTSET, SCANLINES, VGAMODE, HSMODE, PALSEL1 and PALSEL0. There 4 palettes:
CPLD provide all required clocks to FPGA, subcarrier frequency for color coder (master clock 21,4772MHz/3/2 for 50% duty cycle), address decoder like 74x139 and joypad inputs like 74x368. FPGA bypass VGAMODE dipswitch to CPLD, but I don't know why. Also, FPGA require 2 signals form CPLD, but my PPU FPGA version does not have any visible reactions on it.
That's all for now. Ask your questions.