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PostPosted: Mon Jun 29, 2015 10:06 am 
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Joined: Mon Jul 02, 2012 7:46 am
Posts: 759
I'm looking into basically building my own Sync Strike, because $40 is way more than what I'm willing to pay for essentially nothing more than an LM1881 breakout board, but I'm stuck a bit trying to understand the sync signal logic. The LM1881 doesn't output HSYNC, but you can derive HSYNC from VSYNC and CSYNC, and this is where it gets confusing. There are posts online indicating that HSYNC is (C NAND V) AND C, but this seems like the exact opposite of what it should be, as sync pulses are active-low, right? So, for the following waveforms:

Code:
C--___---_-_-_--

V--___----------

H--------_-_-_--


the truth table would be

C V H
0 0 1
0 1 0
1 0 1
1 1 1

which is (C NOR V) OR C. The NAND solution seems to be based on the assumption that the sync pulses are active-high, which doesn't seem to be the case. Can anybody more familiar than me with this stuff clarify which is correct?

Edit: fixed the truth table


Last edited by qwertymodo on Mon Jun 29, 2015 12:05 pm, edited 1 time in total.

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PostPosted: Mon Jun 29, 2015 10:58 am 
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Joined: Sun Apr 13, 2008 11:12 am
Posts: 6280
Location: Seattle
Hsync and Vsync occur in both active-low and active-high forms. (X11 modelines refer to those as "-Hsync" and "+Hsync") I've only ever seen Csync in the active-low form, but there's no reason you couldn't have the opposite.

I've only ever looked as RS170/NTSC csync; When I still had access to a Sun (which uses csync instead of separate) or SGI (which uses sync-on-green) I never thought to stick an oscilloscope on their output, but here's what's true for RS170/NTSC csync:

* The falling edge represents the start of the hsync pulse
* The low-passed value represents vsync.

Here's an ASCII diagram:
Code:
__---------------------------
__---------------------------  <- upper margin (back porch)
__--~~~~~~~~~~~~~~~~~~~~~~---
__--~~~~~~~~~~~~~~~~~~~~~~---
__--~~~~~~~~~~~~~~~~~~~~~~---  <- active field
__--~~~~~~~~~~~~~~~~~~~~~~---
__--~~~~~~~~~~~~~~~~~~~~~~---
__---------------------------
__---------------------------  <- lower margin (front porch)
___________________________--  <- vsync
^^ ^         ^             ^
|  |         |             right margin (front porch)
|  |         active field
|  left margin (back porch, also colorburst)
hsync


Alternatively, some video sources generate what's called "Serration vsync", which looks like this:
Code:
_---------------_------------
__---------------------------
__--~~~~~~~~~~~~~~~~~~~~~~---
__--~~~~~~~~~~~~~~~~~~~~~~---
__--~~~~~~~~~~~~~~~~~~~~~~---
__--~~~~~~~~~~~~~~~~~~~~~~---
__--~~~~~~~~~~~~~~~~~~~~~~---
__---------------------------
_---------------_------------  <- so-called "equalization" pulse
_______________-____________-  <- vsync is also serrated


NTSC nominally has 3 scanlines of equalization before and after the 3 scanlines of vsync. I think the extra pulses are there to make sure the highpass filter doesn't stop hsync's edge detector from working.


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PostPosted: Mon Jun 29, 2015 11:28 am 
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Joined: Mon Jul 02, 2012 7:46 am
Posts: 759
Ok, so that information is definitely helpful, but I'm not sure if it really answers my question (or maybe it does and I'm just not understanding). In the context of feeding NTSC CSync into an LM1881 sync separator to derive HSync and VSync for a VGA monitor (or in my case a StarTech PEXHDCAP capture card using VGA input), assuming that it supports 15kHz/240p, like my capture card does, does my active-low logic assumption hold true, and does the logic H = (C NOR V) OR C correctly derive HSync from CSync/VSync, since the LM1881 only outputs VSync and not HSync? I keep finding references to (C NAND V) AND C (example here), which doesn't seem right to me for active-low signals (but it DOES seem right if it was active-high).


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PostPosted: Mon Jun 29, 2015 11:42 am 
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Joined: Sun Apr 13, 2008 11:12 am
Posts: 6280
Location: Seattle
Years ago I built a simple PS1→RGBHV adapter usign an LM1881 and an XOR gate. (I did HSYNC = XNOR(CSYNC,VSYNC) ) The SVGA projector my dorm had in the basement was just fine with it...

Applying deMorgan's to (+C NAND +V) AND +C yields (-C NOR -V) NOR -C

Your digitizer may also just simply accept csync as though it were hsync.


Last edited by lidnariq on Mon Jun 29, 2015 8:43 pm, edited 1 time in total.

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PostPosted: Mon Jun 29, 2015 12:03 pm 
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Joined: Mon Jul 02, 2012 7:46 am
Posts: 759
Derp, I screwed up transcribing my truth table from paper, but the formula still works. H is low when C is low and V is high.

Code:
C--___---_-_-_--

V--___----------

H--------_-_-_--


C V H
0 0 1
0 1 0
1 0 1
1 1 1

(C NOR V) OR C
(0 NOR 1) OR 0
(0) OR 0
0

Edit for anybody searching this in the future: Ignore this, it doesn't work, I misunderstood lidnariq's posts. For now, the PEXHDCAP seems totally fine just feeding it CSYNC as HSYNC, so I'll probably just leave it at that. I know the Sync Strike uses a single 7400 quad NAND to derive HSYNC from the LM1881, but I still haven't figured out the right logic combination (though from lidnariq's comment I suspect it's probably just a simple XOR, which seems backwards because it should be an XNOR, but in order to make an XNOR out of NAND you need 5... so my best guess is they're doing it backwards and somehow getting away with it >_<).


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