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PostPosted: Mon Jul 04, 2016 12:12 pm 
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So, I know CPLD are available, but it's complicated to use, requires the usagae of advanced software whose maitaining is in itself a problem, and there is no widely accepted chip that has guaranteed posterity (actually no electronic chip ever does, but heh, some more than others).

The PAL22V10 on the other hand is simple and extremely versatile. It also is 5V TTL compatible, however it comes with limitations, there can not be more than 10 flip-flops per chip. There cannot be more than 22 inputs and 10 outputs, and if a flip-flop is used in any output then every output must be a flip-flop, i.e. a whole chip is either combinational or synchronous as a whole. (*) Back when I wrote this topic, I knew squat about PALs, but now that I actually know them (at least better) I think it is possible to emulate the MMC1 perfectly with 4 PAL22V10 chips, and it does not require any other chips (exept maybe a SRAM backup specialized circuit).

The MMC1 needs 4 registers of 5-bits, so this takes up 2 chips (sequential). It also need output logic (combinational) and the 5-bit shift register (sequential). So a full MMC1 will take up 4 chips, if I am not mistaken. It might be possible to use other chips instead for parts of this, but since you have to buy PAL22V10s anyway, it's simpler to use them exclusively and not use any chip of the 74 series for instance.

In the case of a CHR-RAM board such as a SGROM or SNROM clone, the 2 middle MMC1 registers becomes useless if CHR-RAM bankswitching is not used (which is only the case in Romancia), and as such a chip can be removed, the MMC1 can be emulated with only 3 PAL 22V10 chips.

If it is somehow acceptable that writes to the shift register actually writes to the register directly, then the input shift register chip can be ruled out. This means a MMC1 in 3 chips for CHR-ROM, or 2 chips for CHR-RAM.

So it is probably possible to get a MMC1 with a relatively low number of relatively highly available chips, after all. That gus in the thread I linked to who says it needed "dozen" of PAL22V10 chips was definitely wrong.

EDIT: So there is it finally, the shema/diagram of what I mean. It takes one more chip than expected, so 5 PAL22V10s for a full MMC1! I am 90% sure this is technically feasible, however I might have messed up.

The function of the chips are as following:
  • IC1 = Shift register. PAL is in sequential mode
  • IC2 = Register 0 and 3. PAL is in sequential mode
  • IC3 = Register 1 and 2 . PAL is in sequential mode (note, they are in this order because it's more practical for the schematic, but they could be made to be 0, 1, 2, 3 easily if required).
  • IC4 = Output logic for control signals and PRG-ROM higher adresses. PAL is in combinational mode.
  • IC5 = Output logic for higher CHR-ROM adresses (this is essentially a multiplexer that implement 4k bankswitching) PAL is in combinational mode.
When CHR-banking is not used, IC3 and IC5 can be removed completely, and we gat a 3-chip MMC1. If CHR-ROM is used, but only 8k bankswitching is needed, then IC5 can be removed, and we get a 4-chip MMC1. If less PRG and CHR ROM are on board, it might become possible to combine IC4 and IC5. If the shift register can be bypassed (i.e. grabage values in the registers are tolerable during the 5-write sequence), then IC1 can be removed.

A major issue is that the state at reset is not defined, therefore any bank can be mapped to the RESET/NMI/IRQ vector.

Code:
 PPU A10 -----------------------------------------------------------------------------------------------+
 PPU A11 ----------------------------------------------------------------------------------------------+|
 PPU A12 ---------------------------------------------------------------------------------------------+||
        +----------------------------------------------------+                                        |||
        |    IC1 PAL22V10                                    |        IC2 PAL22V10                    |||     IC4 PAL22V10
        |   .`````\/`````.                                   |       .`````\/`````.                   |||    .`````\/`````.
  M2 ---+---|> CLK/IN1   |                                   +-------|> CLK/IN1   |                   ||+----| IN1        |
  (unused) -| IN2    IO1 |---> Parallel out D0 --------+-----|-------| IN2    IO1 |-->(reg3 D0) ---.  |+-----| IN2    IO1 |---> CIRAM A10
  /ROMSEL  -| IN3    IO2 |---> Parallel out D1 --------|+----|-------| IN3    IO2 |-->(reg3 D1) ---.`-|------| IN2    IO2 |---> PRG /CE
  CPU R/W  -| IN4    IO3 |---> Parallel out D2 --------||+---|-------| IN4    IO3 |-->(reg3 D2) ---.`-|------| IN2    IO3 |---> WRAM CE
  CPU D0   -| IN5    IO4 |---> Parallel out D3 --------|||+--|-------| IN5    IO4 |-->(reg3 D3) ---.`-|------| IN2    IO4 |---> PRG A14
  CPU D7   -| IN6    IO5 |---> Parallel out D4 --------||||+-|-------| IN6    IO5 |-->(reg3 D4) ---.`-|------| IN2    IO5 |---> PRG A15
  (unused) x| IN7    IO6 |---x Ctr D0 (internal only)  ||||| |    +--| IN7    IO6 |-->(reg0 D0) ---.`-|------| IN2    IO6 |---> PRG A16
  (unused) x| IN8    IO7 |---x Ctr D1 (internal only)  ||||| |  +-|--| IN8    IO7 |-->(reg0 D1) ---.`-|------| IN2    IO7 |---> PRG A17
  (unused) x| IN9    IO8 |---x Ctr D2 (internal only)  ||||| |  |+|--| IN9    IO8 |-->(reg0 D2) ---.`-|------| IN2    IO8 |<--- /ROMSEL
  (unused) x| IN10   IO9 |---- Parallel load enable ---|||||-|--|||--| IN10   IO9 |-->(reg0 D3) ---.`-|------| IN2    IO9 |<--- CPU A13
  (unused) x| IN11  IO10 |---x (unused)                ||||| |  ||| x| IN11  IO10 |-->(reg0 D4) --+ `-|------| IN2   IO10 |<--- CPU A14
  (unused) x| IN12       |                             ||||| |  ||| x| IN12       |               |CPU|R/W --| IN2        |
            `............`                             ||||| |  |||  `............`               |   |      `............`
                                                       ||||| |  |||                               |   | 
                                                       ||||| |  |||   IC3 PAL22V10                |   |       IC5 PAL22V10
                                                       ||||| |  |||  .`````\/`````.               |   |      .`````\/`````.
                                                       ||||| +--|||--|> CLK/IN1   |               |   +------| IN1        |
                                                       +||||----|||--| IN2    IO1 |-->(reg1 D0) --|----------| IN2    IO1 |--> CHR A12
                                                        +|||----|||--| IN3    IO2 |-->(reg1 D1) --|----------| IN3    IO2 |--> CHR A13
                                                         +||----|||--| IN4    IO3 |-->(reg1 D2) --|----------| IN4    IO3 |--> CHR A14
                                                          +|----|||--| IN5    IO4 |-->(reg1 D3) --|----------| IN5    IO4 |--> CHR A15
                                                           +----|||--| IN6    IO5 |-->(reg1 D4) --|----------| IN6    IO5 |--> CHR A16
                                                                ||+--| IN7    IO6 |-->(reg2 D0) --|----------| IN7    IO6 |--x (unused)
   CPU A14 -----------------------------------------------------|+---| IN8    IO7 |-->(reg2 D1) --|----------| IN8    IO7 |--x (unused)
   CPU A13 -----------------------------------------------------+----| IN9    IO8 |-->(reg2 D2) --|----------| IN9    IO8 |--x (unused)
                                                           (unused) x| IN10   IO9 |-->(reg2 D3) --|----------| IN10   IO9 |--x (unused)
                                                           (unused) x| IN11  IO10 |-->(reg2 D4) --|----------| IN11  IO10 |--x (unused)
                                                           (unused) x| IN12       |               +----------| IN12       |
                                                                     `............`                          `............`


Last edited by Bregalad on Fri Mar 24, 2017 7:25 am, edited 1 time in total.

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PostPosted: Wed Jul 06, 2016 4:32 am 
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Have you seen this one :


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PostPosted: Wed Jul 06, 2016 1:15 pm 
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Farid, that PCB is only approximately 67% of an MMC1. (Sadly.) It only supports H/V mirroring, it only supports 16+16F PRG banking (and as a result it ignores writes with D7 set), it doesn't support 8K CHR banking, and it doesn't deserialize the register writes.

There's a weird trace that shouldn't be there, also:
Attachment:
tj05-error.jpg
tj05-error.jpg [ 28.6 KiB | Viewed 2498 times ]


CHR banking will do something wrong unless $A000 & 8 is the same as $C000 & 4.


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PostPosted: Wed Jul 06, 2016 1:42 pm 
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Not mentionning it is a lot more chips (9 instead of 5).

Apparently PAL22V10 are limited in the sense that funtions can only be made by selecting I think 4 or 5 of the 22 available inputs, I am not sure whether a MMC1 implementation like the one I showed respect this limitation or not. The most complex part would be do decode the "Parallel write" signal, it needs to be enabled when the counter is 0, and when the CPU write to a range included in the ROMSEL signal. At worst, the unused pin can be used to create a 2-stage logic here, but that would delay the register writes by 1 cycle since the PAL is in synchronous clocked mode.


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PostPosted: Wed Jul 06, 2016 2:01 pm 
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Bregalad wrote:
Not mentionning it is a lot more chips (9 instead of 5).
Well, 74xxxs are still cheaper than PAL22V10s. For the portions of the logic that can trivially be mapped to 74xxx parts it's almost certainly a better idea.

Quote:
Apparently PAL22V10 are limited in the sense that functions can only be made by selecting I think 4 or 5 of the 22 available inputs, I am not sure whether a MMC1 implementation like the one I showed respect this limitation or not.
No? It's a giant AND-OR array; each output is OR(intermediate products), and each intermediate product is AND(any subset of all 22 inputs and inversion of same 22 inputs). Each output has a varying number of terms that can be ORed together, ranging from 8 (for pins 23 and 14) to 16 (for pin 19)

... Also, I'm pretty certain that each of the ten outputs can be independently switched between "latching" and "combinatorial"; otherwise they wouldn't be a suitable replacement for the 16R4 and similar parts.
Lattice PALCE22V10 datasheet wrote:
Any [output] macrocell can be configured as combinatorial by selecting the multiplexer path that bypasses the flip-flop (S1 = 1). In the combinatorial configuration, the feedback is from the pin.


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PostPosted: Mon Jan 23, 2017 8:52 am 
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I rev-ed schematics. Can you please dump the PAL? (PIN14 is input!)

Image


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PostPosted: Mon Jan 23, 2017 5:44 pm 
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The PAL clearly is just serving as a 5x 1-of-2 multiplexer.


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PostPosted: Sat Jan 28, 2017 10:10 am 
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U mean:
Code:
CHR-A12 <= REG1.D0 WHEN PPU-A12=0 else REG2.D0;
CHR-A13 <= REG1.D1 WHEN PPU-A12=0 else REG2.D1;
CHR-A14 <= REG1.D2 WHEN PPU-A12=0 else REG2.D2;
CHR-A15 <= REG1.D3 WHEN PPU-A12=0 else REG2.D3;
CHR-A16 <= REG1.D4 WHEN PPU-A12=0 else REG2.D4;
?


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PostPosted: Sat Jan 28, 2017 11:00 am 
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Exactly.


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PostPosted: Sat Jan 28, 2017 6:26 pm 
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Could the board, that gave me problems in that thread, have the mapper implemented based in the logic of this cartridge?


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PostPosted: Sat Jan 28, 2017 8:16 pm 
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this rom not standard mmc1.
I dumped.


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PostPosted: Sun Jan 29, 2017 3:17 am 
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Fisher wrote:
Could the board, that gave me problems in that thread, have the mapper implemented based in the logic of this cartridge?

I rev-ed this PCB - this board is 100% compatible with MMC1, the external OR gate helps switching between two ROMs. Their pinout are quite different (A16 instead of !OE)
Image


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PostPosted: Sat Feb 18, 2017 8:01 am 
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Thanks for the schematics!
That's great!! :D
krzysiobal wrote:
this board is 100% compatible with MMC1

I'm sorry to say I think it doesn't. :-(
Here is a quick summary of my "fight" with this board:

After modifying it to add a PRG-RAM, these were the results I got with The legend of Zelda:
The intro, name entry and after many tries I finally could get into gameplay.

I got similar results with Metroid.
I got this and this after I added this circuit to try to externally decode the PRG RAM and this circuit to try to protect the PRG RAM (or should I say W-RAM?).
Fortunatelly, Lidnariq suggested this circuit to fix that mirroring bug, but I just couldn't find the parts to build one and end up getting a Famicom original game to do my translated repro.

However, the same board worked just fine with Chip'n Dale (the first one) and with Bionic Commando (Should I try Strider on it? Megaman 2 just got the title screen corrupted, but played fine).
I have a similar board with Stealth ATF on it, and saw a Double Dragon and Ninja Gaiden cartridges from the same manufacturer that may (or may not) be using this same board (maybe it's the same from Stealth ATF, that has only one PRG-ROM).
If someone is curious, the cartridge originally looked like this.

Maybe the pirate designers were trying to cut a little costs by not including parts of the mapper that were not used on the games they were releasing?
Or they may have simply misunderstood the inner workings of the mapper...
This also leads me to think that some MMC1 games can be somewhat easily hacked to UxROM or even CNROM.


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PostPosted: Fri Mar 24, 2017 7:20 am 
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I think it should be possible to simulate a MMC1 with maybe only 2 or 3 of Atmel ATF750C chips. Those seems to be in-between CPLDs and PALs; Unlike most CPLDs they are retro-compatible with the 22V10 and uses 5V logic, but they allow for up to 60 "hidden pins". There's still a limit of maximum 10 actual outputs per chip. MMC1 needs 12 output pins and 10 input pins, so in the best case 2 ATF750C chips will be needed. That still sounds like a pretty good deal. Typically if possible I'd do the 1st line of my schematic using an 750C and the second line using a second, so that boards using CHR-RAM could leave out the second chip entierely and have an almost-fully functionnal MMC1 with a single chip.

Atmal also produces ATF2500C chips wich seems more powerful than 750C, maybe one of those can simulate a MMC1 alone ? The main advantage is that they don't require the level shifters nor surface-mounted packages that any other CPLD in the world is going to need. The only disadvantage is that were 100% dependant on Atmel for manufacturing those parts and they could be discontinuited any day Atmel feels like it. But that's also the case of all other CPLDs, only the 22V10 seems like a really generic programmable logic that is interchangeable between manufacturers.


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PostPosted: Fri Mar 24, 2017 8:26 am 
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Bregalad wrote:
I think it should be possible to simulate a MMC1 with maybe only 2 or 3 of Atmel ATF750C chips. Those seems to be in-between CPLDs and PALs; Unlike most CPLDs they are retro-compatible with the 22V10 and uses 5V logic, but they allow for up to 60 "hidden pins".

These "hidden pins" are like CPLD macrocells, which hold a bit of state or control a muxed output, correct? If so, it's a 10-output CPLD.

I checked your count of 12 outputs against the pinout. Several MMC1 configurations would fit in 10 outputs:
  • SGROM: 6 (PRG A17-14 and /CE, VRAM A10)
  • SLROM: 11 (SGROM + CHR A16-12); would fit with 128K PRG ROM
  • SKROM: 12 (SLROM + WRAM +CE)
  • SNROM/SUROM: 8 (SGROM + WRAM +CE, WRAM /CE or PRG A18)
  • SOROM/SXROM: 10 (SUROM + WRAM A14-13)

From the datasheet:
Quote:
Low-power Edge-sensing 'L' Option with 1 mA Standby Current

How would this interact with battery save?

Quote:
All input and I/O pins on the ATF750C(L) have programmable “pin-keeper” circuits. If activated, when any pin is driven high or low and then subsequently left floating, it will stay at that previous high or low level.

The wheels on the open bus go round and round...


EDIT: SXROM address line identification has been corrected


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