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PostPosted: Fri Jun 17, 2016 9:47 pm 
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2A03 register map http://wiki.nesdev.com/w/index.php/2A03 says $4018 through $FFFF is available to the Game Pak but CPU memory map http://wiki.nesdev.com/w/index.php/CPU_memory_map says cartridge space is $4020-$FFFF. So are they in conflict?


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PostPosted: Fri Jun 17, 2016 9:59 pm 
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Because three APU test registers were later discovered at $4018-$401A. These aren't accessible during normal operation but only on a modified NES.


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PostPosted: Fri Jun 17, 2016 10:32 pm 
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So, it needs fixing.
tepples wrote:
Because three APU test registers were later discovered at $4018-$401A. These aren't accessible during normal operation but only on a modified NES.

Link/explain? Why isn't this in the wiki yet? found: http://wiki.nesdev.com/w/index.php/CPU_ ... escription …more a Single Version of Truth problem.

(Hmm, guess this means I should probably avoid mapping $4009, $400D…unless the Visual folks actually checked that out.) http://wiki.nesdev.com/w/index.php/File:Apu_address.jpg

(edit, edit, re-edit)

$4009, $400D, $401B-$401F do not seem to have enables on the linked (alleged, file's CPU revision not marked) 2A03G. Doesn't really mean anything about the 2A07, I guess?


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PostPosted: Sat Jun 18, 2016 12:20 am 
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I mean, it's a little wordy to be precise here:
Read-only registers could be placed safely anywhere from $4000-$4014, and $4018-$FFFF, unless the user has a 2A03G and has tied pin 30 high (in which case $401B-$FFFF).
Write-only registers wouldn't overlap with other functions if they were placed at $4009, $400D, or $4018-$FFFF, unless 2A03G (in which case $4018 and $4019 are still ok but $401A isn't).

Really stretching... there's also the vestigial (broken, dummied out) M2-based IRQ generator in the original 2A03, which was at $401C-$401F.


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PostPosted: Sat Jun 18, 2016 12:36 am 
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So I should map a cycle-timed IRQ to 401C-401F in the ultimate mapper, got it. We know which register was which?


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PostPosted: Sat Jun 18, 2016 1:02 am 
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lidnariq wrote:
there's also the vestigial (broken, dummied out) M2-based IRQ generator in the original 2A03, which was at $401C-$401F.

Wow, was the NES really gonna have a proper built-in IRQ feature? That would've been so cool... I wonder why they gave up on that.


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PostPosted: Sat Jun 18, 2016 1:44 am 
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Tokumaru- It was so broken. It feels like someone had been given a week at most, with no or minimal testing, to scribble in a corner of the masks they were going to use. I think the bits within each byte are backwards, and the R/W logic decoding is definitely backwards. And in Quietust's sim I've never managed to frob nodes high or low to get it to actually count.

The real question in my mind is, given the number of silicon revisions they went through, why didn't they fix it? I guess it's a much more incompatible change than just "adding tonal noise mode" or whatever other changes we know of.

Myask- :)

Certainly $401C-$401E were the 24-bit counter (little-endian), and both readable and writable. But $401F is a full eight bits wide, not a counter, and I'm having/had the hardest time tracing anything down. (The only clear thing is that $401F & $01 controls whether the IRQ flag can signal the CPU) There was also some funny behavior in $4016 and $4017 pertaining to it. There might have been an automatic reload value? I see two S-R latch structures in each bit.


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PostPosted: Sat Jun 18, 2016 2:58 am 
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Hmm. Been a long time since I hit gates-to-logic, so I had to [re]acquaint myself with types of flip-flops.

It seems there are quite a few ways to assemble a D flip-flop (which tends to be the typical way to assemble a binary counter), some including 2 (or 3) SR latches…but I don't have the decap to look at. [Where] do we have a version of our decap region map for the 2A03? What do you mean, "original" 2A03?

Is the half-baked clock-counter in the earlier revision here-"unknown region" bit Quietust mentions there?

edit: the above isn't very coherent. I initially thought that rp2a03g was a revision of some sort. I don't have a Waldo[Wally] to compare to try playing Where's Waldo[Wally] with the interrupt logic, but I would like to know where this mystery region is to at least try to look at, though I can't see signal-tracing finding me a disconnected element, so…


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PostPosted: Sat Jun 18, 2016 7:29 am 
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Does TCRF take dummied-out console hardware elements, or will everything but game content get reverted?


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PostPosted: Sat Jun 18, 2016 7:40 am 
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Myask wrote:
What do you mean, "original" 2A03?

"Original" 2A03 as in "RP2A03", as opposed to "RP2A03G". It's the version of the CPU that's present in some arcade units, and it totally lacks the logic to produce the alternate "looped" noise.

The extra IRQ counter-related stuff mentioned above is physically disconnected - most of the traces going into and coming out of that part of the chip were cut off (including power/GND), so it is totally nonfunctional and cannot be enabled by any means.

lidnariq wrote:
Read-only registers could be placed safely anywhere from $4000-$4014, and $4018-$FFFF, unless the user has a 2A03G and has tied pin 30 high (in which case $401B-$FFFF).

In reality, no user would ever tie pin 30 high, because if they did then the joypad registers would stop working - when pin 30 is low, only $4015 reads come from inside the chip (and $4016/$4017 come from outside), but when pin 30 is high, all of $4000-$401F reads come from inside the chip, so $4016 and $4017 just return "open bus".

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PostPosted: Sat Jun 18, 2016 12:36 pm 
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Myask wrote:
I initially thought that rp2a03g was a revision of some sort.
It is.

Quote:
I would like to know where this mystery region is to at least try to look at, though I can't see signal-tracing finding me a disconnected element
It's not in the 2A03G one. There's the raw pictures here (where it's in the upper-right corner), and there's the sim that Quietust made, which is shaved down to just the raw chunk of logic. (I had to go back to the raw pictures to figure out what would have generated /enable.)

As Quietust points out, this is purely academic: there's no way to fix it on the original die. But it is a funny little puzzle.


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PostPosted: Sat Jun 18, 2016 7:35 pm 
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Yeah, was getting a bit foggy last nightmorning. Not sure where I saw someone post 2a03[g] that made me think it was implicit.

Linking this here for easier reference: lidnariq's original checking into the IRQ-gen dead block, with nodes noted…

Quietust wrote:
lidnariq wrote:
Read-only registers could be placed safely anywhere from $4000-$4014, and $4018-$FFFF, unless the user has a 2A03G and has tied pin 30 high (in which case $401B-$FFFF).

In reality, no user would ever tie pin 30 high, because if they did then the joypad registers would stop working - when pin 30 is low, only $4015 reads come from inside the chip (and $4016/$4017 come from outside), but when pin 30 is high, all of $4000-$401F reads come from inside the chip, so $4016 and $4017 just return "open bus".

zzo38's idea of tying it to pin 7 (CPU_ADDR3) to turn it off when using $4016-7 was interesting. I take it you never followed up on that?

Hmm…24 bits is really long for a cycle counter. Almost ten seconds' worth on NTSC(~9.4), but if $4017 reads really reset it, then you'd have to not use 2p to get that.

Colorblindness isn't helping any. You have a node for W401F? Can you tell if the counter would have halted at 0?

[idle, uninformed guesses/speculation/design] TTSS SRAE: E = enable, A = acknowledge R = use special reload from d3-7 S = index for special reloads T = type of reload (user-set # (ignore S), scanline (2^S lines), frame (2^S frames), seconds? (might just have integer multiples for seconds))
and have special reloads come from some period table like the APU does.
Was also considering having a "freeze" bit, since it'd be a little annoying to load a counter while it's running. Or a "set reload to counter"/"set counter to reload" pair of bits.


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PostPosted: Sun Jun 19, 2016 2:13 am 
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Sounds like we should stay consistant and say $4020-$ffff are to cartridge's use, because $4000-$401f are definitely used, even if part of it it's a huge mess that was given up in the release versions of the CPU. I don't think a couple of extra registers to the cartridge's use would make any difference for a mapper design, period.


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PostPosted: Sun Jun 19, 2016 3:56 am 
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Myask wrote:
Hmm…24 bits is really long for a cycle counter. Almost ten seconds' worth on NTSC(~9.4), but if $4017 reads really reset it, then you'd have to not use 2p to get that.


It sounds more like a watchdog timer. In fact, that's how the VS and Playchoice reset their watchdog timer, by reading $4017. Can we be sure this for an IRQ instead of a much less interesting reset?


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PostPosted: Sun Jun 19, 2016 5:49 am 
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That and $4017 on a Vs. is player 1.


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