MMC1 double writes blocking - explicit register or CPU R/W ?
Posted: Wed Mar 29, 2017 12:14 pm
So it's a well doccumented fact that MMC1 ignores double writes, only the first write cycle of a multi-write cycle is acknownledge. With a raw 6502 processor only incrementing, decrementing and shifting instructions can do double writes outside of the stack page, and nothing can do triple or more writes in a row. However there is conflicting info about how it manages to have this "feature".
In this post dating back to 2012, infinitelives is very confident that the MMC1 has an explicit register who remembers if the last operation, and only allows the shift register to shift or be reseted if the last operation was a read. The range would be ignored - even a write on $0000-$7fff would prevent a consecutive write to $8000-$ffff to affect the shift registers - even though such a situation cannot happen with the CPU. He said he explicitely tested the MMC1, and that R/W cannot possibly be used as a clock.
On the wiki there is the following "evidence" :
Finally, even in the possibility that somehow Infinitelives was wrong and that R/W is actually used to clock the registers, I think the MMC1 wouldn't work at all if this was done, because the R/W line would be changing when Phi2 is low, and the adress/data lines could be unstable at that point. So we could end up having a MMC1 shift register randomly written to or reset due to the MMC1 behaving on incorrect data before the A13, A14, D0 and D7 lines are ready. This leads me to belive infinitelives is right and Kevtris is wrong, despite the fact his statement is more recent (2015).
In this post dating back to 2012, infinitelives is very confident that the MMC1 has an explicit register who remembers if the last operation, and only allows the shift register to shift or be reseted if the last operation was a read. The range would be ignored - even a write on $0000-$7fff would prevent a consecutive write to $8000-$ffff to affect the shift registers - even though such a situation cannot happen with the CPU. He said he explicitely tested the MMC1, and that R/W cannot possibly be used as a clock.
On the wiki there is the following "evidence" :
This is in total contradictions with infinitelives' finding. Since the evidence is weak (just "this guy said that") I would be tempted to reject it as being fake, but I am still withing to understand the truth and cannot ignore any possibility.#nesdev IRC chat, 2015/05/23. kevtris: "I think I figured out why the MMC1 ignores the second write. It seems to be because it uses R/W as a clock, and it stays low for 2 cycles, instead of pulsing so only the first is written."
Finally, even in the possibility that somehow Infinitelives was wrong and that R/W is actually used to clock the registers, I think the MMC1 wouldn't work at all if this was done, because the R/W line would be changing when Phi2 is low, and the adress/data lines could be unstable at that point. So we could end up having a MMC1 shift register randomly written to or reset due to the MMC1 behaving on incorrect data before the A13, A14, D0 and D7 lines are ready. This leads me to belive infinitelives is right and Kevtris is wrong, despite the fact his statement is more recent (2015).