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 Post subject: Request for new mappers
PostPosted: Wed May 31, 2017 2:55 am 
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Adding in a VIA/CIA style timers on the IRQ would be really nice. Even if its just 1 16bit timer and a TOD.


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PostPosted: Wed May 31, 2017 3:21 am 
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The 6525 is hard to find, let alone in large quantities. What is the benefit of this timer (not counting the additional circuitry for i/o operations)?

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PostPosted: Wed May 31, 2017 3:57 am 
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I was thinking the timers would be emulated in the CPLD/FPGA, rather than drop a 6526A ( you would need the 2Mhz version + extra circuit to drop the CPU clock down to a 50/60hz signal ) on the board.

TOD is useful for doing things like Make X happen in 5 seconds, or 10 minutes. at 50fps 5 seconds is 250 frames, 60fps 5 seconds is 300.. 5 minutes at 50fps is 15,000 and 60fps is 18,000. So having a TOD to do the counting keep the times locked when porting regions. Could be shown in game to aid Speed Runners, or you can use it time various aspects, destruction countdowns, round times, quest timers etc and change things like difficulty, or make items drop to change the game play on extended play sessions.
Show a on-screen msg for a second, like when you enter a town in a RPG or damage.

Timers have a lot of uses, for extra note timings in music engines, for generating random vales based upon button presses, you can use 2 timers where 1 is an inverted cycle counter to get stable rasters. You can even execute code in the Timers to jump to timer routines to get 100% super stable ;), you can use them to profile your code more accurately, you can use them to see how much frame time is left and to make calls on if you update things or not for frame time management.

You can use the Timers to act as a separate thread, in that you normally have a NMI and Main, you can get a NMI, IRQ and Main threads.


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PostPosted: Wed May 31, 2017 4:04 am 
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I'd like 4kb bankswitching granularity, for 4+4+4+4 and 16kb fixed. Also, a hardware zlib decompressor chip.


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PostPosted: Wed May 31, 2017 7:24 am 
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Hmm.. would something like this suffice? 0,6-0,5 eur / piece depending on quantity. Might be cheaper (or more suitable*) things out there. http://www.mouser.com/ds/2/302/PCF85063TP-842236.pdf

*Several channels of timers ticking in seconds (or fractions) would be more pragmatic than a ss:mm:hh:dd:mm:yy format. Depending on the application, of course. In any case, i'd look for timer chips with low power consumption, usually meant for mobile devices like cameras and what not.

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PostPosted: Wed May 31, 2017 7:46 am 
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Oziphantom wrote:
TOD is useful for doing things like Make X happen in 5 seconds, or 10 minutes. at 50fps 5 seconds is 250 frames, 60fps 5 seconds is 300.. 5 minutes at 50fps is 15,000 and 60fps is 18,000. So having a TOD to do the counting keep the times locked when porting regions.

Keeping intervals consistent across TV systems can also be done entirely in software. A couple of my games divide NMI by five or six depending on TV system, producing an internal timer that ticks every tenth of a second. (In Thwaite, see uses of gameTenthSecond and gameSubTenth; in RHDE, see uses of time_tenths and time_subtenths.) The resulting values of current decisecond and current frame within decisecond let me schedule updates that happen 5 or 10 times per second, spreading out the work load across multiple frames. Both games assign periodic 10 Hz tasks for frames 0, 1, 2, 3, and 4 of each tenth, with nothing scheduled for 5 because PAL.

As for making the name of a town appear and disappear, Thwaite does something similar, making "tips" disappear after fifty tenths. (See uses of tipTimeLeft.) RHDE does something similar for alert boxes between rounds. (See uses of delay_y_tenths.)

As for music timing, these games use the Pently music engine, which adds rows-per-minute to a 16-bit counter and compares it to 3606 on NTSC or 3000 on PAL. (See uses of pently_rows_per_beat and tempoCounterLo.)

And just as The Simpsons already did it in western animated sitcoms, Super Mario Bros. already did it on NES. Speedrunners of that game and Super Mario Bros. 2 (J) are familiar with a 21-frame counter that schedules parts of the engine to run, which is why a new run for most levels must be 21 frames shorter than the previous run to make any improvement. It gets shortened to 18 frames on PAL.


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PostPosted: Wed May 31, 2017 8:21 am 
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Well the RTC could probably stand in for a TOD, although that one doesn't have the full Alarm set ( its has minute and 30seconds ) and pulses the IRQ pins, rather than waiting for latch means you would need extra management to avoid a double trigger.

That being said WDC do still make PIA and VIA, sadly they no longer make CIA but ACIA which are not as useful for this case(no timers no TOD :( ). Pricey though, but come in DIP http://www.westerndesigncenter.com/wdc/w65c22-chip.cfm you could re-purpose the 2 8bit Data Ports one for PPU banking, and one for CHR banking. This would give you read/write registers you could use to control what the current banks are.


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PostPosted: Wed May 31, 2017 9:05 am 
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I'm not sure DIP is an advantage here though. It's great for one-off projects and mods or socketed swapables, but SMD:s are generally faster even at home (unless they're too small), and you'd want to reduce the time manual labour takes. 8 dollars is pricey (as you said) if you just want the timers, but if you can use the rest, it might be worth it?

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PostPosted: Wed May 31, 2017 10:30 am 
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calima wrote:
I'd like 4kb bankswitching granularity, for 4+4+4+4 and 16kb fixed. Also, a hardware zlib decompressor chip.


How about a second 6502 type CPU at 20mhz with shared RAM to communicate with the NES CPU giving you all the computing power you could want. The NES CPU would just be the middle man between the NES I/O and the much faster on cartridge CPU. Or use whatever kind of CPU you want and do the same thing. Use the audio input and connect whatever audio hardware you want too.


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PostPosted: Wed May 31, 2017 10:55 am 
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There are lots of low cost (<$1) microcontrollers with a built in RTC. A little glue logic may be needed, but one could set up any number of simple/complex timing IRQs if an mcu is handling the task.

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Last edited by infiniteneslives on Wed May 31, 2017 11:15 am, edited 1 time in total.

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PostPosted: Wed May 31, 2017 11:10 am 
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Quote:
How about a second 6502 type CPU at 20mhz

You could, but what about cost per board? You'd essentially build a single board computer with fixed software. That doesn't sound consumer friendly.
EDIT: i see W65C02S goes for 5,89 EUR per unit for a batch of 100.

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PostPosted: Wed May 31, 2017 11:46 am 
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FrankenGraphics wrote:
You'd essentially build a single board computer with fixed software. That doesn't sound consumer friendly.

Super Game Boy, Super FX GSU, and SA-1 say hi.


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PostPosted: Wed May 31, 2017 11:50 am 
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Stuffing a 6502 core into a cheap FPGA is probably cheaper than getting a new 6502 in silicon :/

If you just want a Programmable Interval Timer with a very long count, you might just use the design of the broken one inside the original 2A03.


A hardware decompressor doesn't really make sense to me. You'd have to implement it in an FPGA, so you'd have to add 3V translation. Once you've added 3V translation you can get large parallel NOR flash for cheap, and huge Guaranteed Good Die parallel NAND flash for roughly the same. And at that point the challenge becomes "making enough content" rather than "how do I compress this data to fit in a small ROM"

That said, the idea of grafting an SA-1 into an NES still amuses. The S-DD1 is architecturally incompatible, though.


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PostPosted: Wed May 31, 2017 12:07 pm 
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Or skip majority of parallel level translation and put it data in dirt cheap serial flash which gets copied into PRG-RAM for execution.

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PostPosted: Wed May 31, 2017 12:21 pm 
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infiniteneslives wrote:
dirt cheap serial flash which gets copied into PRG-RAM for execution.

Booting how? What's your current plan toward this?


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