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 Post subject: Dual-PPU system design
PostPosted: Fri Jun 09, 2017 1:02 pm 
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I don't actually have any interest in implementing this. I just think it's fun to think about.

I can see two practical problems with running two 2C02 PPUs in a master/slave configuration. The biggest is that the missing dot on every other frame when rendering is enabled would cause the PPUs to drift out of sync over time, 30 pixels for each second in which one PPU's rendering is enabled and the other's not. Another is that you'd need two separate sets of CHR RAM and nametable memory, one for each PPU, unless you can design some sort of multiplexer circuit.

If you have solutions for these, I'd be interested to see a new topic about them.
The first problem is easily solved: overlap PPU registers.
If PPU1 has its decoder as M2 AND /A15 AND /A14 AND A13 AND /A3, and PPU2 has its decoder as M2 AND /A15 AND /A14 AND A13 AND A4, then writes to $2011 will turn on both at the exact same time. And writes to $2000...$2007 address only PPU1, and writes to $2018-$201F address only the other.

Of course, there's no way to get OAM DMA into the second one. I'm not clear just how problematic this is: whether a layer of background-colored sprites is actually useful. If we don't need to accommodate sprites, then "just" giving PPU2 8 KiB of RAM for 4scr nametables and background tiles seems like an obvious choice.

I think the exciting thing about the dual-PPU circuit is that it could have been easily done in the 1980s, even if it wasn't.

(As far as emulation ... I'd be much more excited to see a dual-APU tracker that could target Vs. System / VT03 / Donkey Kong.)


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PostPosted: Sat Jun 10, 2017 4:06 am 
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Of course, there's no way to get OAM DMA into the second one.

Why just not map both of their registers at $2000-$2007 and add another two bit latch which stores info, which PPU (PPU1/PPU2/BOTH) should be used when accessing $2000-$2007?

That way you can write to them simulatenously and both can have OAM_DMA.


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PostPosted: Sat Jun 10, 2017 9:51 am 
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Yeah. If we're making something compatible with the NES instead of the Famicom, we could even use OUT1 and OUT2 instead of A3 and A4.

However, if we are trying to explicitly support sprites on the second PPU, then the design of what to provide it with becomes more complex. I guess the simplest option is just to provide a flat 16 KiB of addressable RAM, but maybe Memblers's GTROM CHR-RAM design would be a better choice.


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PostPosted: Sat Jun 10, 2017 9:52 am 
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Sounds good to me!


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