Hm. I tried analyzing that fusemap using jed2eqn, and it complained. So I looked closer ... and it's using an operational mode that Lattice's datasheet doesn't define.
those last two bits are called SYN and AC0. Lattice only explains what 01, 10, and 11 mean.
National's datasheet does
mention that the two function independently:
The SYN bit controls whether a device will have any registered outputs (SYN=0) or will be purely combinatorial (SYN=1). The SYN bit determines whether device pins 1 and 11 are used as the clock and global TRI-STATE control inputs (SYN=0) or whether they are ordinary inputs (SYN=1). The AC0 bit selects between the "Small-PAL" mode and the "Medium/Registered-PAL" modes. The function of the AC1 bits depends on the state of the AC0 bit. In "Small-PAL" mode (AC0=0), the AC1 bit in each [output logic macrocell] determines whether the associated device pin is an output (AC1=0) or an input (AC1=1)
It then continues to give an example of permissible modes and also excludes the 00 combination.
SYN=0 means that pin 1=M2 serves as the clock, and pin 11=PRGA21 controls whether the outputs can serves as /OE ? Er. But:
AC0=0 means that all pins are always an input or an output and ignores pin 11.
Well, small wonder that the ADC doesn't work.
AC1 exists per output; there are 8 bits. Bits 2120 through 2127 are b'00001100'; this means the following:
Pins 19 & 12 are always an output, have 8 AND terms, the output of the register is not presented on the pin, but the output of the register is available inside the AND-OR plane.
Pins 18,17,16, & 13 are always outputs, have 8 AND terms, the output of the register is not presented on the pin, but the value on the next-higher-numbered pin is available inside the AND-OR plane.
Pins 15 & 14 are always inputs, have 8 AND terms, the output of the register would be presented on the pin, the value on the next-higher-numbered pin is available inside the AND-OR plane.
XOR exists per output; there are 8 bits. Bits 2048 through 2055 are b'01100001', meaning that pins 18, 17, and 12 are inverted relative to the logic from the AND-OR plane.
Meanwhile, the fusemap includes an 8-byte "user signature" in bits 2056 through 2119, which happens to be ASCIIZ: "GAL16V8\x0"