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PostPosted: Tue Jun 20, 2017 3:21 pm 

Joined: Sun Jun 12, 2011 12:06 pm
Posts: 446
Location: Poland
I encountered some trouble while implementing mapper 163 in hardware (FPGA)

The trouble was with the CHR RAM bank switch feature at scanline 128. I read the discussion hint at this page and the solution
Whenever PPU A13 transitions from 0 to 1, latch the current value of PPU A9. When the 'c' bit is on, use that latched value instead of PPU A12 as the input to CHR RAM A12.

sounds simple. Unfortunately I could not test it because my FPGA does not have PPU_A9 wired (and probably no other carts have it as well because CHR bank granularity below 1 KB is not common).

My first idea was to count scanlines by counting PPU_A12 rises as MMC3 does (8 rises per scanline). However, MMC3 have scanline counter that is initialized in VBLANK and then it counts down. I did not have any good idea how to detect proper moment to clear the counter (not clearing it or clearing after counting to 240*8 resulted in vertical movement of the moment that banks are switched).

I ended in counting rising edges of PPU_A13. When it counts to 43 * 127 - 8, the bank is changed.
8 is subtracted because without doing it, bank was switched in mid-scanline. Counter is cleared when CPU accesses $FFFA (NMI vector). It works very good, however I would like to ask if there is any way to do the same without refering to CPU for condition to reset and using only PPU_A10/A11/A12/A13

PostPosted: Tue Jun 20, 2017 3:57 pm 

Joined: Sun Apr 13, 2008 11:12 am
Posts: 7812
Location: Seattle
Does M2 count as a CPU signal or just a timebase?

Waiting for PPU A13 to go idle would be the "obvious" answer.

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