Jaleco SS88006 and ADPCM ICs

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lidnariq
Posts: 8692
Joined: Sun Apr 13, 2008 11:12 am
Location: Seattle

Jaleco SS88006 and ADPCM ICs

Post by lidnariq » Fri Aug 04, 2017 6:09 pm

I was taking a closer look at the various boards in NesCartDB that use the SS88006 and I think previous documentation about how the ADPCM IC playback works is probably wrong.

(For the record: boards JF-23, -24, -25, -29, -37 without battery+PRGRAM; -27, -40 with)

I'm have this strong hunch that writes to $F003 are latched on (at least) two of the pins on the SS88006, and those pins are connected to the µPD775x /PLAY and /RESET pins ... CPU D2 through D7 are connected to µPD775x I0 through I5

From tracing pictures of the PCB, I was able to get half the SS88006's pinout:

Code: Select all

    M2 -> | 01  42 | -- +5
CPUA12 -> | 02
CPUA13 -> | 03
CPUA14 -> | 04
PRGA16 <- | 05
PRGA15 <- | 06  37 | -> /START
PRGA14 <- | 07
PRGA13 <- | 08
PRG/OE <- | 09
PRGA17 <- | 10
 ?a18? <- | 11
 CPUA1 -> | 12
 CPUA0 -> | 13
 CPUD0 -> | 14
 CPUD1 -> | 15
 CPUD2 -> | 16
  ?D3? -> | 17
   R/W -> | 18
/ROMSL -> | 19
  /IRQ <- | 20
   Gnd -- | 21
It'd be really nice if someone had the parts on hand to take a closer look ...

Ice Man
Posts: 366
Joined: Fri Jul 04, 2014 2:34 pm

Re: Jaleco SS88006 and ADPCM ICs

Post by Ice Man » Tue Apr 03, 2018 12:35 pm

Code: Select all

                   SS88006
					    ___  ___
			   M2 -> | 01\/42 | -- +5
		 CPU A12 -> | 02  41 | --  
		 CPU A13 -> | 03  40 | --  
		 CPU A14 -> | 04  39 | --  
		 PRG /CE <- | 05  38 | -> /RESET
		 PRG A15 <- | 06  37 | -> /START
		 PRG A14 <- | 07  36 | --  
		 PRG A13 <- | 08  35 | <- PPU /RD
		 PRG A16 <- | 09  34 | --  
		 PRG A17 <- | 10  33 | --  
		 PRG A18 <- | 11  32 | -> CHR A16
		  CPU A1 -> | 12  31 | --  
		  CPU A0 -> | 13  30 | -> CHR A13
		  CPU D0 -> | 14  29 | --  
		  CPU D1 -> | 15  28 | -> CHR A14 
		  CPU D2 -> | 16  27 | -> CHR A15
		  CPU D3 -> | 17  26 | --  
		 CPU R/W -> | 18  25 | -> 74'32 Pin 05
		 /ROMSEL -> | 19  24 | <- PPU A12
			 /IRQ <- | 20  23 | <- PPU A11 
			  GND -- | 21  22 | <- PPU A10 
					    --------
			 
			 
					  74'32												       D7755C
					  __  __												      __  __
			    M2 |01\/14| VCC		    						 PRG D6 |01\/18| PRG D5
			    M2 |02  13| NC		   				 		  PRG D7 |02  17| PRG D4
		       NC |03  12| NC 		       						 GND |03  16| PRG D3
		  PPU /RD |04  11| /ROMSEL or NC (J4)				     GND |04  15| PRG D2
 SS88006 Pin 25 |05  10| /ROMSEL or NC (J3)	     	    To R2 |05  14| /START
		  CHR /CE |06  09| /ROMSEL or NC (J3)		   	 Cart 46 |06  13| GND
			   GND |07  08| NC			 				          BUSY |07  12| X1
					  ------								          /RESET |08  11| X2
														                  GND |09  10| VCC
															                    ------
Some more information I was able to get by routing a Terao no Dosukoi Oozumou.
It's not much, nor do I know if it's correct but I hope that helps for now.
Will work on it more tomorrow. Feel free to complete or work on it if anyone knows more about the pinouts.

EDIT1: Updated
Last edited by Ice Man on Fri Apr 06, 2018 11:09 am, edited 2 times in total.

Ice Man
Posts: 366
Joined: Fri Jul 04, 2014 2:34 pm

Re: Jaleco SS88006 and ADPCM ICs

Post by Ice Man » Fri Apr 06, 2018 11:09 am

Updated a little bit. This is all I could get from my board. Hope this helps a little bit.

J3 and J4 confuse me a little bit though.
J4 is NC while J3 is bridged connecting the 74HC32 pins to pin 19 of the SS88006.

lidnariq
Posts: 8692
Joined: Sun Apr 13, 2008 11:12 am
Location: Seattle

Re: Jaleco SS88006 and ADPCM ICs

Post by lidnariq » Fri Apr 06, 2018 11:35 am

My visual RE'ing for the 74'32 has this:

Code: Select all

                 74'32
                .--\/--.
             M2 |01  14| VCC
             M2 |02  13| d/ROMSEL
            dM2 |03  12| d/ROMSEL
        PPU /RD |04  11| dd/ROMSEL
        PPU A13 |05  10| /ROMSEL
        CHR /CE |06  09| /ROMSEL
            GND |07  08| d/ROMSEL
                '------'
J3/J4 select between the original /ROMSEL or the doubly-delayed /ROMSEL respectively.

Likewise, J5/J6 select between M2 and the singly-delayed M2.

I'm not clear why PPU A13 and PPU /RD go to both the SS88006 and the 74'32, though. Nor how CHR is supposed to work when the 74'32 is unpopulated and J1 is fitted—I don't see how PPU /RD gets to the CHR-ROM in this case.

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