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PostPosted: Wed Aug 16, 2017 7:12 am 
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Location: リムルダール Rimuldar
みなさんが積極的な発言をしてくれていて作者だった私はとてもうれしい.


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PostPosted: Wed Aug 16, 2017 3:13 pm 
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Joined: Tue Aug 15, 2017 1:07 pm
Posts: 16
lidnariq wrote:
Easy things first:

What you've traced shows this functionality:
Code:
           +--------+++- not yet known
           |        |||
 A~[1... ..up PPPP Puuu]
            | |||| |
            | ++++-+---- 32KB PRG slice (i.e. ROM A15 through A19)
            +----------- very likely A20 = ROM1 vs ROM2


The remaining functions must exist in the remaining four bits:
1- one bit must select between H/V nametable layout. This will be which of the pins on the two GD74LS174s connects to "pin 2" on the 74LS153.
2- one bit must disable writes to the HY6264 RAM. This will be which of the pins on the two GDLS174s connect to ... some of the pins on the 74LS32.
3- one bit must select between 16K and 32K PRG. This will be which of the pins on the two GD74LS174s connects to "pin 14" on the 74LS153.
4- one bit must select between the upper and lower half when in 16K PRG mode. This will be two of pins 3-6 on the 74LS153.

Either way, one of these two kazoo fragments should give you a valid dump:
Code:
 board <- {
   mappernum = 100, /* Note: No mapper yet assigned to this board. 100 is just a "known bad" value. */
   cpu_rom = {
      size_base = 16 * mega, size_max = 16 * mega, banksize = 0x8000
   },
   ppu_rom = {
      size_base = 0, size_max = 0, banksize = 0
   },
   ppu_ramfind = false, vram_mirrorfind = true
};

function cpu_dump(d, pagesize, banksize) {
  for (local i = 0; i < pagesize; i += 1) {
    cpu_write(d, 0x8000|(i*8), i);
    cpu_read(d, 0x8000, 0x4000);
    cpu_read(d, 0xc000, 0x4000);
  }
}

OR
Code:
 // Same as above, but change the similar line to:
    cpu_write(d, 0x8207|(i*8), i);



First of all thanks to all who helped, I changed the firmware and was able to do the dump by creating a script with the above codes,
a 2Mb file was generated but when trying to emulate it the following error appeared:

Attachment:
Untitled-21.jpg
Untitled-21.jpg [ 130.66 KiB | Viewed 428 times ]


Ps.
I tried the mapper 63 and it did not work too

Following is the files generated with the two passages of code "Cpu write"

Attachment:
82in1.nes [2 MiB]
Downloaded 27 times


Attachment:
82in1_.nes [2 MiB]
Downloaded 27 times


Last edited by flaviocaste on Wed Aug 16, 2017 3:38 pm, edited 1 time in total.

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PostPosted: Wed Aug 16, 2017 3:37 pm 
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Joined: Sun Jun 12, 2011 12:06 pm
Posts: 264
Location: Poland
What do you think about it? Just wild guess.

Image Image

Code:
 A~[1... ..wP PPPP PPMm]
           || |||| ||||
           || |||| |||+-- mirroring (0=V, 1=H)
           || |||| ||+-- PRG mode (0=16K, 1=32K)
           |+-++++-++--- PRG bank (lowest bit ignored in 32K mode)
           +------------ CHR-RAM write protection (0=disabled, 1=enabled)



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PostPosted: Wed Aug 16, 2017 3:48 pm 
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Joined: Mon Dec 12, 2011 8:15 pm
Posts: 362
flaviocaste wrote:
lidnariq wrote:
Easy things first:

What you've traced shows this functionality:
Code:
           +--------+++- not yet known
           |        |||
 A~[1... ..up PPPP Puuu]
            | |||| |
            | ++++-+---- 32KB PRG slice (i.e. ROM A15 through A19)
            +----------- very likely A20 = ROM1 vs ROM2


The remaining functions must exist in the remaining four bits:
1- one bit must select between H/V nametable layout. This will be which of the pins on the two GD74LS174s connects to "pin 2" on the 74LS153.
2- one bit must disable writes to the HY6264 RAM. This will be which of the pins on the two GDLS174s connect to ... some of the pins on the 74LS32.
3- one bit must select between 16K and 32K PRG. This will be which of the pins on the two GD74LS174s connects to "pin 14" on the 74LS153.
4- one bit must select between the upper and lower half when in 16K PRG mode. This will be two of pins 3-6 on the 74LS153.

Either way, one of these two kazoo fragments should give you a valid dump:
Code:
 board <- {
   mappernum = 100, /* Note: No mapper yet assigned to this board. 100 is just a "known bad" value. */
   cpu_rom = {
      size_base = 16 * mega, size_max = 16 * mega, banksize = 0x8000
   },
   ppu_rom = {
      size_base = 0, size_max = 0, banksize = 0
   },
   ppu_ramfind = false, vram_mirrorfind = true
};

function cpu_dump(d, pagesize, banksize) {
  for (local i = 0; i < pagesize; i += 1) {
    cpu_write(d, 0x8000|(i*8), i);
    cpu_read(d, 0x8000, 0x4000);
    cpu_read(d, 0xc000, 0x4000);
  }
}

OR
Code:
 // Same as above, but change the similar line to:
    cpu_write(d, 0x8207|(i*8), i);



First of all thanks to all who helped, I changed the firmware and was able to do the dump by creating a script with the above codes,
a 2Mb file was generated but when trying to emulate it the following error appeared:

Attachment:
The attachment Untitled-21.jpg is no longer available


Ps.
I tried the mapper 63 and it did not work too

Following is the files generated with the two passages of code "Cpu write"

Attachment:
The attachment 82in1.nes is no longer available


Attachment:
The attachment 82in1_.nes is no longer available



82in1_.nes [2 MiB] is ok. change mapper 100 to mapper 63 ,working nestopia,same game not working ,60.64...


Attachments:
82in1__001.png
82in1__001.png [ 6.88 KiB | Viewed 419 times ]
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PostPosted: Wed Aug 16, 2017 3:58 pm 
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Joined: Tue Aug 15, 2017 1:07 pm
Posts: 16
krzysiobal wrote:
What do you think about it? Just wild guess.

Image Image

Code:
 A~[1... ..wP PPPP PPMm]
           || |||| ||||
           || |||| |||+-- mirroring (0=V, 1=H)
           || |||| ||+-- PRG mode (0=16K, 1=32K)
           |+-++++-++--- PRG bank (lowest bit ignored in 32K mode)
           +------------ CHR-RAM write protection (0=disabled, 1=enabled)



For me it looks like a professional job !

Thank you.


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PostPosted: Wed Aug 16, 2017 4:01 pm 
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Joined: Tue Aug 15, 2017 1:07 pm
Posts: 16
zxbdragon wrote:
flaviocaste wrote:
lidnariq wrote:
Easy things first:

What you've traced shows this functionality:
Code:
           +--------+++- not yet known
           |        |||
 A~[1... ..up PPPP Puuu]
            | |||| |
            | ++++-+---- 32KB PRG slice (i.e. ROM A15 through A19)
            +----------- very likely A20 = ROM1 vs ROM2


The remaining functions must exist in the remaining four bits:
1- one bit must select between H/V nametable layout. This will be which of the pins on the two GD74LS174s connects to "pin 2" on the 74LS153.
2- one bit must disable writes to the HY6264 RAM. This will be which of the pins on the two GDLS174s connect to ... some of the pins on the 74LS32.
3- one bit must select between 16K and 32K PRG. This will be which of the pins on the two GD74LS174s connects to "pin 14" on the 74LS153.
4- one bit must select between the upper and lower half when in 16K PRG mode. This will be two of pins 3-6 on the 74LS153.

Either way, one of these two kazoo fragments should give you a valid dump:
Code:
 board <- {
   mappernum = 100, /* Note: No mapper yet assigned to this board. 100 is just a "known bad" value. */
   cpu_rom = {
      size_base = 16 * mega, size_max = 16 * mega, banksize = 0x8000
   },
   ppu_rom = {
      size_base = 0, size_max = 0, banksize = 0
   },
   ppu_ramfind = false, vram_mirrorfind = true
};

function cpu_dump(d, pagesize, banksize) {
  for (local i = 0; i < pagesize; i += 1) {
    cpu_write(d, 0x8000|(i*8), i);
    cpu_read(d, 0x8000, 0x4000);
    cpu_read(d, 0xc000, 0x4000);
  }
}

OR
Code:
 // Same as above, but change the similar line to:
    cpu_write(d, 0x8207|(i*8), i);



First of all thanks to all who helped, I changed the firmware and was able to do the dump by creating a script with the above codes,
a 2Mb file was generated but when trying to emulate it the following error appeared:

Attachment:
Untitled-21.jpg


Ps.
I tried the mapper 63 and it did not work too

Following is the files generated with the two passages of code "Cpu write"

Attachment:
82in1.nes


Attachment:
82in1_.nes



82in1_.nes [2 MiB] is ok. change mapper 100 to mapper 63 ,working nestopia,same game not working ,60.64...



It worked perfectly with nestopia 1.40, thanks to all who have helped and forgive my lack of knowledge.
This rom is not available on the internet, if it is convenient we can divulge it.

Thank you.


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PostPosted: Wed Aug 16, 2017 4:05 pm 
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Joined: Mon Dec 12, 2011 8:15 pm
Posts: 362
Quote:


82in1_.nes [2 MiB] is ok. change mapper 100 to mapper 63 ,working nestopia,same game not working ,60.64...



It worked perfectly with nestopia 1.40, thanks to all who have helped and forgive my lack of knowledge.
This rom is not available on the internet, if it is convenient we can divulge it.

Thank you.[/quote]

perfectly? nono,try 60,64 game.ninja?


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PostPosted: Wed Aug 16, 2017 4:28 pm 
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Joined: Tue Aug 15, 2017 1:07 pm
Posts: 16
zxbdragon wrote:
Quote:


82in1_.nes [2 MiB] is ok. change mapper 100 to mapper 63 ,working nestopia,same game not working ,60.64...



It worked perfectly with nestopia 1.40, thanks to all who have helped and forgive my lack of knowledge.
This rom is not available on the internet, if it is convenient we can divulge it.

Thank you.


perfectly? nono,try 60,64 game.ninja?[/quote]


I did the dump with mapper 60,64 and it appeared "CPU Jam" in the nestopia,
the only mapper that showed the menu of the game was 63.

Attachment:
Untitled-1.jpg
Untitled-1.jpg [ 81.98 KiB | Viewed 404 times ]


Thanks.


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PostPosted: Wed Aug 16, 2017 4:32 pm 
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Joined: Tue Feb 14, 2017 9:50 am
Posts: 43
He meant that you should try to play game #60 or #64 and see if they boot up or softlock.


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PostPosted: Wed Aug 16, 2017 4:39 pm 
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Joined: Tue Aug 15, 2017 1:07 pm
Posts: 16
MLX wrote:
He meant that you should try to play game #60 or #64 and see if they boot up or softlock.



Really, 60,64 does not start, is there anything we can do?


Thanks.


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PostPosted: Wed Aug 16, 2017 4:41 pm 
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Joined: Sun Apr 13, 2008 11:12 am
Posts: 6535
Location: Seattle
Krzysiobal: I suspect that this cart uses A0 in the reset detection circuit...


Cart's menu is first 16 KiB. If registers are cleared on power-up, then whichever bit that is must go 0:16K NROM and 1:32K NROM
Found a stub (at ROM offset 0x0127) that copies CHR from PRG to PPU.
Found a table at ROM offset 0x306 that appears to be the lower 8 bits of what's written to get the bank that contains CHR. (Bottom 2 bits always 0) Upper 8 bits are always $F1. Writes to $F000 to switch back to the menu.
Found a table at ROM offset 0x0358 that is the upper 8 bits of the CPU address to copy CHR from.
Found a table at offset 0x03AA that is the series of 16-bit (big-endian) words written to the banking register to switch into game ... except that the loader adds 0x200 to the address.

Both $F01A and $F01B appear in the table, implying to me that the A0 bit (&1) becomes PRG A14 and the A2 bit (&4) A1 controls 16K vs 32K. Leaving A1 A2 for mirroring control.


flaviocaste: We'll probably need to allocate a new (UNIF/NES2) mapper for it.


Last edited by lidnariq on Thu Aug 17, 2017 9:52 am, edited 1 time in total.

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PostPosted: Wed Aug 16, 2017 4:57 pm 
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Joined: Sun Jun 12, 2011 12:06 pm
Posts: 264
Location: Poland
I've just added mapper63 definition to FCEUX in the way I described it and all games works, so maybe your mapper 63 in nestopia is invalid.
Image Image Image Image

BTW. It's first time I add mapper in FCEUX and I am not familiar with this SDK, for example I don't know how to add CHR-RAM protection.

Quote:
Krzysiobal: I suspect that this cart uses A0 in the reset detection circuit...


I just think that the diode is to make quick discharge of capacitor after power switch.


Attachments:
63.cpp [1.63 KiB]
Downloaded 25 times
fceux_support_for_82in1.zip [1.26 MiB]
Downloaded 21 times


Last edited by krzysiobal on Wed Aug 16, 2017 5:16 pm, edited 1 time in total.
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PostPosted: Wed Aug 16, 2017 5:00 pm 
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Joined: Sun Apr 13, 2008 11:12 am
Posts: 6535
Location: Seattle
No, no, this cart isn't mapper 63. That's just another mapper that zxbdragon observed is extremely similar.



Quote:
I just think that the diode is to make quick discharge of capacitor after power switch.
Why would it need the diode at all in that case? The overvoltage protection diodes in the various parts will discharge the capacitor on power failure quite quickly.


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PostPosted: Wed Aug 16, 2017 5:21 pm 
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Joined: Sun Jun 12, 2011 12:06 pm
Posts: 264
Location: Poland
Quote:
Why would it need the diode at all in that case? The overvoltage protection diodes in the various parts will discharge the capacitor on power failure quite quickly.

Maybe LS series (74LS174) does not have clamp diodes or maybe not to risk high current flow over internal chip protecting diodes (it's electrolite cap so it can store quite lot of energy).

I know one famous famiclone multicart (5-in-1 Codemasters's BIC) which has similar reset circuit but without diode installed (there is place for diode to be soldered) and it does not start properly on every console power up.

---

I think there are only clamp diodes to the ground, but not to VCC in LS chips - one guy decapped a lot of 74 chips from different families and rev-ed schematics. Only in CMOS (HC) there are clamp diodes to VCC and GND.
https://project5474.org/index.php?title=02


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PostPosted: Wed Aug 16, 2017 5:49 pm 
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Joined: Sun Apr 13, 2008 11:12 am
Posts: 6535
Location: Seattle
krzysiobal wrote:
Maybe LS series (74LS174) does not have clamp diodes or maybe not to risk high current flow over internal chip protecting diodes (it's electrolite cap so it can store quite lot of energy).
Well, then, why is it electrolytic? There's no need for the >1ms time constant if it's just to make sure that the pin is low on first power-up.

... Actually, though, the right answer is to just ask flaviocaste whether the multicart goes back to the menu when he hits the reset button.


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