Well It didn't work!
So this is way too tough than it seems at first even for a simple read operation!
Here are some notes I found out from googling :
I have to use only EPP mode and not SPP or ECP.
Reg5 of Control pin is used for Enabling Bi-directional mode for D0 ~ D7 [pin2 ~ pin9]. So I have to set it to 1 to enable this feature.
Before you can start any EPP cycles by reading and writing to the EPP Data and Address Ports, the port must be configured correctly. In the idle state, an EPP port should have it's nAddress Strobe, nData Strobe, nWrite and nReset lines inactive, high. Some ports require you to set this up before starting any EPP Cycle. Therefore our first task is to manually initialise these lines using the SPP Registers. Writing XXXX0100 to the control port will do this.
The Status Port has one little modification. Bit 0, which was reserved in the SPP register set, now becomes the EPP Time-out Bit.
The EPP Timeout bit we have already discussed. When this bit is set, the EPP port may not function correctly. A common scenario is always reading 0xFF from either the Address or Data Cycles. This bit should be cleared for reliable operation, and constantly checked.
1. Program reads EPP Data Register. (Base + 4)
2. nData Strobe is asserted if Wait is Low (O.K. to start cycle)
3. Host waits for Acknowledgment by nWait going high
4. Data is read from Parallel Port Pins.
5. nData Strobe is de-asserted.
6. EPP Data Read Cycle Ends.
Visual Basic for Electronics Engineering Applications : page 419 :
The control signals used to perform the bus cycles are fairly simple. As a
example, consider an address write cycle. To begin an address write cycle, the
host places an 8-bit address on_ADO-AD7 and pulls Write (indicating that the
host is doing a write operation) and AStrb (indicating that the information on
ADO - AD7 is an address) low. The peripheral device corresponding to the
address responds by setting Wait high to indicate that it recognizes it's being
addressed and is ready to receive the address byte. Upon seeing Wait go high,
the host de-asserts AStrb. This action signals the peripheral to read and store the
byte on ADO-AD7 to use as the register address for following data cycles. The
peripheral then pulls Walt low to indicate that it's ready for a new bus cycle, and
the host ends the current bus cycle by removing the signals from ADO-AD7 and
setting Write back high.
A data read bus cycle proceeds in much the same manner. The Dstrb and Wait
lines are the handshake signals that coordinate the data transfer, and the state of
the Write line determines whether the bus cycle is a read cycle or a write cycle.