Apparently, NES-ETROM and HVC-ETROM boards can support both 8kb / 64 kbit (6264) and 32kb / 256 kbit (62256) chips, selected by solder pads. This allow this board to support 16 kb total RAM (two small chips) (the only possibility actually used by comercially released games), 40 kb total RAM (one chip each), and 64 kb total RAM (both big chips, suspected to be used by the Sim City prototype).
However, it looks like NES-EKROM / HVC-EKROM boards only supports small SRAM chips (8 kb / 64 kbit) while NES-EWROM only supports big SRAM chips (32 kb / 256 kbit). If it is simple to make a board that support both chip sizes, why are EKROM and EWROM different boards in the first place ? They could have made just a single board that supports both sizes through solder pads.
The only real difference seems to be with pin 26, which is Chip Enable on 8k SRAMs and A13 on 32k SRAMs.
MMC5 carts and 8kb (6264) and 32kb (62256) SRAM chip support
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Re: MMC5 carts and 8kb (6264) and 32kb (62256) SRAM chip sup
I believe that's why.Bregalad wrote:The only real difference seems to be with pin 26, which is Chip Enable on 8k SRAMs and A13 on 32k SRAMs.
1- SRAM +CE comes from the MMC5, and the MMC5 seems to have all the battery circuitry inside it.
2- It's less confusing to have banks 0-3 contain the same 8 KiB of RAM instead of only banks 1 and 3
Now, I haven't heard of more save loss on EWROM boards than on EKROM boards, so the former caution was probably unnecessary, but the second still holds.
Re: MMC5 carts and 8kb (6264) and 32kb (62256) SRAM chip sup
So basically EKROM has an extra enable used as data-loss-protection circuit, that neither ETROM nor EWROM have ? That kind of make sense... but the SRAM data loss has always been a mystery to me (even though I was a victim of that multiple times - no matter whether I pressed Reset or not).
Re: MMC5 carts and 8kb (6264) and 32kb (62256) SRAM chip sup
ETROM uses the extra enable, too. It's only EWROM that's shipped configured for one 32 KiB RAM, without the separate +CE control.
Re: MMC5 carts and 8kb (6264) and 32kb (62256) SRAM chip support
mmc5 supports 2 srams at most, it has the ability to select one 32KB(sram0) or another 8KB(sram1).
if exists sram1, sram0 and sram1 always be 8KB. -- not correct
so the most accurate form is 32K+8K:
write $5113 bit[1:0] to latch the inner sram0 bank.
write $5113 bit[2] to latch the outer sram0/sram1 bank(or sram_cs).
sram0 can be backed by battery, and sram1 doesnt.
but to simplify the logic complexity, i suggest use one single sram(>=64K), and always back up with battery.
so the most accurate form is 32K+8K:
write $5113 bit[1:0] to latch the inner sram0 bank.
write $5113 bit[2] to latch the outer sram0/sram1 bank(or sram_cs).
sram0 can be backed by battery, and sram1 doesnt.
but to simplify the logic complexity, i suggest use one single sram(>=64K), and always back up with battery.