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PostPosted: Thu Nov 23, 2017 4:11 pm 
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I just want to ask to make sure, because the wiki is a bit confusing on this topic.

Is the following correct?
  • 1. Between the CPU and the controller ports / expansion ports on both the NES and Famicom, all 2 x 5 input lines are inverted. Thus a 5V input from the controller pin / expansion port will be read by the CPU as a 0, and 0V will read as 1.
  • 2. The outputs from the CPU ($4016 write D0-2) are not inverted. Sending a 1 from the CPU produces 5V output until $4016 is written again with a 0.
  • 3. The CLK signal is normally 5V, but when the CPU reads $4016 or $4017 it becomes 0V while reading, and then returns to 5V once completed which will clock the shift register (low-to-high transition).
  • 4. The expansion lines and the front controller port are both tied to the same inverting buffer, so it is not the case that one is inverted and the other is not.

The reason I'm confused about this is the expansion port diagrams on the wiki mention inversion for only two cases, and then notate all the controller input data lines with xx which I don't know the meaning of. Controller port pinout doesn't mention how the signals work at all or even just inversion. Then I found this topic with a schematic that looks horribly wrong to me.

Standard controller seems to say this stuff, now that I've kinda sorted it out and can follow what I'm reading but I just want to see if I understand this properly or not.


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PostPosted: Fri Nov 24, 2017 4:32 am 
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rainwarrior wrote:
Between the CPU and the controller ports / expansion ports on both the NES and Famicom, all 2 x 5 input lines are inverted. Thus a 5V input from the controller pin / expansion port will be read by the CPU as a 0, and 0V will read as 1.
Correct, in the Famicom and NES-001 there's a 74'368 inverting the pins from the controller jacks and/or expansion port into the CPU. There's some ASIC in the AV Famicom and NES-101 that does something similar.

Quote:
The outputs from the CPU ($4016 write D0-2) are not inverted. Sending a 1 from the CPU produces 5V output until $4016 is written again with a 0.
Correct.

Quote:
The CLK signal is normally 5V, but when the CPU reads $4016 or $4017 it becomes 0V while reading, and then returns to 5V once completed which will clock the shift register (low-to-high transition).
Basically correct. The behavior is subtly different in the NES and the Famicom.

In the Famicom, the pin floats with a weak pullup. /RD4016 and /RD4017 enable a tristateable inverter from M2, pulling the CLK signals strongly high then low on every cycle that the 2A03 reads from the joysticks.

In the NES, the 2A03's pin is directly connected to the CLK pins on the controllers, and M2 does not affect things; as a result, DPCM bit deletions of the serial port will behave differently.

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The expansion lines and the front controller port are both tied to the same inverting buffer, so it is not the case that one is inverted and the other is not.
Correct.

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then notate all the controller input data lines with xx which I don't know the meaning of.
I've added a call-out in the bit below to try to explain that.


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PostPosted: Fri Nov 24, 2017 2:42 pm 
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Thanks for the confirmation. I'll try to spruce up the wiki a little bit.

lidnariq wrote:
In the Famicom, the pin floats with a weak pullup. /RD4016 and /RD4017 enable a tristateable inverter from M2, pulling the CLK signals strongly high then low on every cycle that the 2A03 reads from the joysticks.

In the NES, the 2A03's pin is directly connected to the CLK pins on the controllers, and M2 does not affect things; as a result, DPCM bit deletions of the serial port will behave differently.

So... does this mean that on the Famicom the CLK signal goes high partway through the cycle (via M2) and on the NES it goes high slightly later when the whole cycle is finished?

How does that affect DPCM bit deletions differently?

Was I correct to assume that CLK is otherwise pulled high at all times?

lidnariq wrote:
rainwarrior wrote:
then notate all the controller input data lines with xx which I don't know the meaning of.
I've added a call-out in the bit below to try to explain that.

So the xx is just trying to indicate that there's a potential bus conflict if two things are connected to the same line?


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PostPosted: Fri Nov 24, 2017 2:55 pm 
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rainwarrior wrote:
So... does this mean that on the Famicom the CLK signal goes high partway through the cycle (via M2) and on the NES it goes high slightly later when the whole cycle is finished?

How does that affect DPCM bit deletions differently?
Ideally, to the best of my knowledge, in the case of a double-read, the two waveforms should look like this:
Code:
Famicom """""""""""""""""_______"""""_______""""""""""""
NES     """"""""""""________________________""""""""""""


Code:
Was I correct to assume that CLK is otherwise pulled high at all [other] times?
Yeah. There's a pullup resistor on the NES that weakly pulls the pin high when the 2A03 is reset.

rainwarrior wrote:
So the xx is just trying to indicate that there's a potential bus conflict if two things are connected to the same line?
I was more thinking that it's neither strictly an input nor an output because it depends on what else is connected.


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PostPosted: Fri Nov 24, 2017 3:59 pm 
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Ah, okay so I had the order backwards (it goes low earlier, rather than high later).

So the double read DPCM case is when a bit deletion read happens one cycle later than a legit read, causing a deletion on the Famicom but not the NES?

Does that also mean instructions with a double read can have a deleted bit on the Famicom but not the NES? (Maybe that only applies to RMW instructions, though? It seems like the read-only instructions aren't capable of doing a double read from the same address?)


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PostPosted: Fri Nov 24, 2017 4:10 pm 
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rainwarrior wrote:
So the double read DPCM case is when a bit deletion read happens one cycle later than a legit read, causing a deletion on the Famicom but not the NES?
Yeah. I don't remember exactly the address pattern that happens during a DPCM deletion, so I don't know exactly how it would go.

I guess that with the NES, you'll only get a single bit deletion, where as things that care about M2, such as the the Famicom and 2C02 $2007 you'll see multiple bits of deletion.

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It seems like the read-only instructions aren't capable of doing a double read from the same address?
I think you're right. (The RMW abs,X instructions do... say X=0, ROL $4017,x should read from and write to $4017 both twice.)


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