|Fixing dency-clone with broken PPU
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|Author:||krzysiobal [ Tue Oct 31, 2017 6:51 pm ]|
|Post subject:||Fixing dency-clone with broken PPU|
I have dendy-clone which looks like that:
All games works (meaning - CPU works properly, CPU-PPU comunication also works) but there is some problem with video rendering - image looks just like internal VRAM would be broken (just some random mosaique with colors matching true colors - so Attribute Table probably is stored/read correctly).
I disabled the internal PPU RAM and wired external RAM but no effect (thought VRAM is broken):
Then I measured some things and what I found is that:
-There is completely no signal on PPU-A7/PPU-A6
-Amplitude on PPU-A8/A5 is two times less than other signals - around 2V (on other pins around 4V)
I thought of any way of recover PPU-A7-PPU-A6. I watched PPU-D, but unfortunatelly those NES-on-CHIP clones does not produce lower 8 address bits on PPU-D prior latching A0-A7 (just like DIP-40 PPU in order to drive `373 external latch)
Any idea how to recover those missing signals? If not, I even thought of adding board with UA6538+VRAM+373 and some address decoder based on !ROMSEL, M2, A14 but:
1. How to clock the external UA6538 so that it uses the same clock as glob-top and no phase drift occurs? There is only external quartz in this NOC board, while all generating circuit is inside glob top.
2. How to wire the external PPU with NOC's CPU? -> `broken` PPU cannot be probably disconnected from NOC CPU, but what about putting TWO PPUs on the same bus at the same memory range (and maybe add some kind of buffer which will cut off second PPU's DATA bus from CPU on reads)
|Author:||krzysiobal [ Wed Dec 20, 2017 7:35 am ]|
|Post subject:||Re: Fixing dency-clone with broken PPU|
I found some time to return to this interesting topic. Some sample game screenshoot looks like that:
I did some measuremens with scope and I was quite wrong at the beginning of my logic analyzer measurements. Here are measures from scope:
PPU A4 - amplitude is very low (~30mV peak-to-peak)
PPU A5 - amplitude is low (~2V pp)
PPU A7 - amplitude is very low (~30mV peak-to-peak)
PPU A8 - amplitude is low (~2V pp)
all other CPU/PPU address/data buses has correct signals. PPU A6 is taken as reference signal. (2V/div in normal mode, 10mV/div in magnified move)
For PPU A4/PPU A7 logic analyzer was not able to detect the signal (and it's barely visible at the scope). Magnyfying to the lowest possible mV division shows that there is very weak signal of around 30 mV pp, but because of noise, the safe region is only around 10 mV.
There are 2 possible solutions:
1. amplify those signals to restore them to proper voltage level
2. recover them from PPU DATA bus (PA8 can't be restored that way).
While 1 might work for PA5/PA8, doing it for those weak signals at PA4 / PA7 might be tricky because the low level of signal is not at 0V, so it would rather require comparing it with reference voltage of precised value (like 1.405V). This probably would still be not immune to noise, so I thought 2 would work better (for PA4/PA5/PA7).
The idea is that PPU in discrete consoles outputs A7-A0 on D7-D0 to latch it in 74*373. For Famiclone-On-Chip this could not work the same way, because the PPU might have all address lines as separate pins. Another difficulty is that ALE signal is not externally present.
I take closer look at data bus of this Famiclone-On-Chip, for example PD5/PA5 just at the beginning of PPU cycle (write cycle). By comparing PD5 just at the moment !WR falls (or just a moment after), it is equal to the A5!
This is good news because this can be used to recover A5 (and A4 & A7 aswell)
More progress soon..
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