rainwarrior wrote:
Between the CPU and the controller ports / expansion ports on both the NES and Famicom, all 2 x 5 input lines are inverted. Thus a 5V input from the controller pin / expansion port will be read by the CPU as a 0, and 0V will read as 1.
Correct, in the Famicom and NES-001 there's a 74'368 inverting the pins from the controller jacks and/or expansion port into the CPU. There's some ASIC in the AV Famicom and NES-101 that does something similar.
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The outputs from the CPU ($4016 write D0-2) are not inverted. Sending a 1 from the CPU produces 5V output until $4016 is written again with a 0.
Correct.
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The CLK signal is normally 5V, but when the CPU reads $4016 or $4017 it becomes 0V while reading, and then returns to 5V once completed which will clock the shift register (low-to-high transition).
Basically correct. The behavior is subtly different in the NES and the Famicom.
In the Famicom, the pin floats with a weak pullup. /RD4016 and /RD4017 enable a tristateable inverter from M2, pulling the CLK signals strongly high then low on every cycle that the 2A03 reads from the joysticks.
In the NES, the 2A03's pin is directly connected to the CLK pins on the controllers, and M2 does not affect things; as a result, DPCM bit deletions of the serial port will behave differently.
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The expansion lines and the front controller port are both tied to the same inverting buffer, so it is not the case that one is inverted and the other is not.
Correct.
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then notate all the controller input data lines with xx which I don't know the meaning of.
I've added a call-out in the bit below to try to explain that.