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PostPosted: Thu May 03, 2018 10:57 pm 
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And now with the rest of the enclosure put together:
https://www.youtube.com/watch?v=pXp97wzkQEE


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PostPosted: Mon May 28, 2018 3:25 pm 
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Finally finished writing the next blog post, which covers the assembly and testing of the main board for the first real prototype:

Building the Nestronic Prototype (Part 3)
http://hecgeek.blogspot.com/2018/05/nestronic-3.html

(Maybe someday I'll blog without a multi-week lag before doing something and having a writeup ready... Someday...)


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PostPosted: Mon May 28, 2018 4:55 pm 
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Quote:
My memory map couldn't support the address ranges used by the NES APU's DMC output, which a handful of games apparently use
Oh. Yeah. Oops.

I wonder what the simplest way is to remap the RAM to available to hold DPCM for the DMA unit to handle.

I'd be tempted to split the 8K into two 4K windows, divided by A14, and enable RAM any time A13 was low. Then there'd be 4K for internal RAM at $0000, mirrored to $8000, and 4K for DPCM at $C000, mirrored under the registers at $4000. (You don't have to worry about a bus conflict on reads from $4015, in case anything does: the 2A03 internally prevents it). But something more complicated is probably nicer anyway.


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PostPosted: Tue May 29, 2018 5:12 pm 
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lidnariq wrote:
Quote:
My memory map couldn't support the address ranges used by the NES APU's DMC output, which a handful of games apparently use
Oh. Yeah. Oops.

I wonder what the simplest way is to remap the RAM to available to hold DPCM for the DMA unit to handle.

I'd be tempted to split the 8K into two 4K windows, divided by A14, and enable RAM any time A13 was low. Then there'd be 4K for internal RAM at $0000, mirrored to $8000, and 4K for DPCM at $C000, mirrored under the registers at $4000. (You don't have to worry about a bus conflict on reads from $4015, in case anything does: the 2A03 internally prevents it). But something more complicated is probably nicer anyway.


Splitting the RAM into two 4K windows is one idea I've considered. Another idea is to simply mirror it at $8000, and make sure I don't allow any addresses into the DMC registers that overlap RAM being used by my program code.

The former idea gives me a simpler memory model, while the latter frees up a little bit extra RAM for this purpose. (Yet another idea would be to add a second SRAM chip, but that would require a lot more signal routing.)


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PostPosted: Tue May 29, 2018 5:27 pm 
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dkonigs wrote:
Another idea is to simply mirror it at $8000, and make sure I don't allow any addresses into the DMC registers that overlap RAM being used by my program code.
Problem is that DPCM DMA can only fetch from $C000-$FFF1¹, so you have to prevent the writes to $40xx from colliding with zero-page usage. But I guess you're only running your own software, so maybe that's acceptable.

¹you can start a DMA at some high address and when it overflows it wraps around—after fetching from $FFFF it will fetch from $8000—but that's just goofy and overlaps with the vectors.

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(Yet another idea would be to add a second SRAM chip, but that would require a lot more signal routing.)
Or replace the 8K RAM with a 32K RAM. Would need only two extra traces over the 8K RAM.


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PostPosted: Tue May 29, 2018 8:23 pm 
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I originally thought the DMC start address could be set so I could wrap around and begin at $8000. But upon double-checking, it seems that's not the case. Thanks for making me double-check.
That being said, I can still mirror my SRAM to $C000-$DFFF and hopefully be okay. My VGM player code is going to have to remap DMC memory blocks anyway, since I can't place them on top of my program ROM, so I'm prepared to deal with that.

I hadn't considered using a 32KB SRAM (or some other size), and splitting it across areas of the memory map, but its also not a bad idea. If done right, it might even make the address decoding glue simpler than mirroring the 8KB SRAM.

I'm definitely going to sketch out all these ideas before I go ahead and make the "Rev B" design changes to my board. Until then, I guess I just can't play the SMB3 soundtrack. :-P


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PostPosted: Thu Jun 28, 2018 7:02 pm 
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If anyone is interested in following along with the actual development, the entire project (code + schematics) has recently been moved up to GitHub:
https://github.com/dkonigsberg/nestronic


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PostPosted: Sat Aug 04, 2018 11:08 pm 
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Since I just finished building revision B of the project design, I threw together an assembly video. It covers the whole process, start-to-finish. Hopefully its decent:
https://youtu.be/UlO0NQTAaJU


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